LUT-Based Fast-Carry Adder Circuit Design

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Solution Overview

Problem

Ripple-carry adders face processing-speed limitations as the number of bits increases, and look-ahead carry adders incur additional complexity and cost due to the need for look-ahead carry generation logic.

Innovation Solution

The implementation of a programmable LUT4 circuit that can operate in either LUT mode or arithmetic mode, using pre-computed values stored in memory cells and multiplexers to generate carry and sum bits efficiently, thereby avoiding the need for complex look-ahead carry generation logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If ripple-carry adder is used, then device complexity is reduced, but processing speed decreases as number of bits increases

Engineering Contradiction:

Improveadder structure complexityVSAvoidprocessing speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent pre-computes and stores carry bit values in memory cells (LUT) before the actual addition operation. This preliminary computation of carry bits allows the adder to avoid the sequential ripple-carry delay, significantly improving processing speed while maintaining relatively simple circuit structure through the use of lookup tables rather than complex look-ahead logic.

Inventive Principle:

Principle #10Preliminary action

2Speed

If look-ahead carry adder is used, then processing speed is improved, but device complexity and cost increase due to look-ahead carry generation logic

Engineering Contradiction:

Improveprocessing speedVSAvoidcarry generation logic complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Instead of implementing complex look-ahead carry generation logic, the patent uses memory cells to store pre-computed carry bit values. This approach copies the results of complex carry calculations into simple memory structures, achieving fast carry bit availability without the structural complexity of traditional look-ahead carry logic circuits.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent replaces expensive and complex look-ahead carry generation logic with simpler memory cell structures that store carry bit values. This substitution uses cheaper, simpler memory elements to achieve the same functional result of fast carry bit provision, reducing overall device complexity and cost.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Speed

If LUT circuit operates in arithmetic mode with pre-computed values, then processing speed is improved, but memory cell storage requirements increase

Engineering Contradiction:

Improveaddition processing speedVSAvoidmemory cell quantity

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The patent segments the addition operation into separate functional components: memory cells store pre-computed carry bit values, while simple logic circuits perform the actual addition using these stored values. This segmentation allows the memory to be optimized for storing only the necessary carry bit information rather than all possible computation results, reducing memory requirements while maintaining fast processing speed.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7685215B1Fast-carry arithmetic circuit using a multi-input look-up table

Publication Date: 2010.03.23 LATTICE SEMICON CORP

AI summary

In one embodiment of the invention, programmable circuits, such as FPGAs, may be used to implement different types of functions, such as a multi-bit adder, using look-up table (LUT) circuits as their building blocks. Efficient generation of carry-out signals and fast-carry generation signals using available SRAM cells in the various embodiments of the LUT circuit can reduce and/or eliminate area-inefficient look-ahead carry logic without a significant delay in signal generation.