Dual-Output LUT Flip-Flop Implementation in FPGAs
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Solution Overview
Problem
Programmable logic devices, such as FPGAs, often face a mismatch in the ratio of combinational logic to flip-flops, leading to unused lookup tables due to a lack of available flip-flops, necessitating a method to accommodate variations in design requirements.
Innovation Solution
Implementing flip-flops within programmable lookup tables by configuring them to include a master latch and a slave latch, with feedback paths formed through multiplexer circuits using transmission gates and logic gates, allowing the LUTs to function as flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ratio of combinational logic to flip-flops is fixed in the CLB structure, then the standard logic storage function is maintained, but LUTs remain unused when designs require more flip-flops than LUTs
Solution Approach 1:
The LUT is configured to perform multiple functions: it can operate as a traditional combinational logic device or be reconfigured to implement flip-flop functionality. By programming the LUT to include a master latch and slave latch with feedback paths, the same hardware resource adapts to different design needs, eliminating the mismatch between logic resources and storage resources.
Solution Approach 2:
The LUT structure is made dynamically reconfigurable through programming. Configuration memory cells control transmission gates and multiplexers to dynamically change the LUT's internal connectivity and logic function, allowing it to transform from a static combinational logic device to a sequential element with feedback paths when needed.
2Quantity of substance
If separate LUTs and flip-flops are used as distinct resources, then the standard CLB architecture is maintained, but the number of available flip-flops is insufficient for designs requiring more storage elements
Solution Approach 1:
The invention merges the functions of LUTs and flip-flops by implementing latch structures directly within the LUT fabric. The master latch and slave latch are integrated into the LUT's multiplexer network, allowing the same programmable logic resource to provide both combinational logic and sequential storage functions, effectively doubling the available flip-flop count without adding separate storage resources.
Data Source
AI summary
Circuits and methods of implementing flip-flops in dual-output lookup tables (LUTs). A flip-flop is implemented by programming a dual-output LUT to include a first function implementing a master latch and a second function implementing a slave latch. An output of the master latch is provided at a first output terminal of the LUT, and an output of the slave latch is provided at a second output terminal of the LUT. The output of the master latch (the first output of the LUT) is coupled to a first input terminal of the LUT, where it drives both the first and second functions. The output of the slave latch (the second output of the LUT) is coupled to a second input terminal of the LUT, where it drives the second function. A clock signal is provided to both first and second functions via a third input terminal of the LUT.