LUT-Free Hardware Accelerator for AI Activation Functions
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Solution Overview
Problem
Existing hardware architectures for artificial intelligence (AI) face challenges in supporting a wide range of activation functions efficiently due to high storage requirements, access latencies, and increased costs associated with lookup tables (LUTs), as well as accuracy loss and implementation complexity in conventional approximation methods.
Innovation Solution
A software programmable, LUT-free hardware accelerator that decomposes activation functions into basic arithmetic operators and executes them on compute units, eliminating the need for costly frontend decoders and complex register file multiplexers, while providing programmability and high-precision compute capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If lookup table (LUT) based approach is used for activation functions, then computation accuracy is improved, but storage area increases and access latency increases
Solution Approach 1:
The patent extracts the activation function computation from the traditional LUT-based memory access approach and implements it using pure arithmetic operations (multiply and accumulate) on compute units. This removes the need for large storage structures while maintaining computational accuracy through mathematical approximation of the activation functions.
Solution Approach 2:
The patent replaces the mechanical memory access system (LUT) with an arithmetic computation system (MAC operations). Instead of storing pre-computed values in memory and accessing them, the system computes activation functions in real-time using arithmetic operators, thereby eliminating storage area requirements while maintaining computational accuracy.
2Measurement precision
If lookup table (LUT) based approach is used for activation functions, then computation accuracy is improved, but access latency increases
Solution Approach 1:
The patent extracts the activation function computation from the traditional LUT-based memory access approach and implements it using pure arithmetic operations (multiply and accumulate) on compute units. This removes the need for large storage structures while maintaining computational accuracy through mathematical approximation of the activation functions.
Solution Approach 2:
The patent replaces the mechanical memory access system (LUT) with an arithmetic computation system (MAC operations). Instead of storing pre-computed values in memory and accessing them, the system computes activation functions in real-time using arithmetic operators, thereby eliminating storage area requirements while maintaining computational accuracy.
3Adaptability or versatility
If multi-ported LUTs are used to support sharing across multiple channels, then functionality is improved, but cost increases
Solution Approach 1:
The patent implements a universal compute unit architecture that can execute multiple activation functions through software programmability. Instead of requiring separate hardware ports for different channels, a single compute unit can be reconfigured via software to support any activation function, providing multi-functional capability without the cost of multi-ported hardware structures.
Solution Approach 2:
The patent employs dynamic reconfiguration of the compute unit through software control to adapt to different activation function requirements. The system can dynamically switch between different activation functions by loading different computational kernels, eliminating the need for static multi-ported hardware designs and reducing overall system cost.
4Device complexity
If conventional approximation approach is used for activation functions, then implementation complexity is reduced, but accuracy loss occurs
Solution Approach 1:
The patent optimizes the approximation parameters (coefficients and order of polynomial expansions) to achieve high accuracy while maintaining simple implementation. By carefully selecting and tuning these parameters, the system achieves accurate activation function approximation using basic arithmetic operations, avoiding the need for complex hardware structures.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that identifies a type of a first activation function, identifies a derivative level of the first activation function, and generates a first instruction based on the type of the first activation function and the derivative level of the first activation function. The technology also includes an accelerator having logic coupled to one or more substrates, the logic including a compute engine including a plurality of arithmetic operators, a multiplexer network coupled to the compute engine, and a controller coupled to the multiplexer network, the controller to detect the first instruction, decode the first instruction to identify the first activation function, and drive the multiplexer network to form first connections between two or more of the plurality of arithmetic operators in accordance with the first activation function, wherein the first connections are to cause the compute engine to conduct the first activation function.