LUT Input Assignment Optimization for PLD Timing Paths
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Solution Overview
Problem
Existing programmable logic device implementations often fail to meet timing objectives due to propagation delays exceeding specified clock periods, particularly in critical timing paths, which can be misidentified by static timing analysis tools.
Innovation Solution
The method involves determining the topological level of look-up tables (LUTs) in a programmable logic device, identifying LUTs on critical timing paths, swapping inputs to improve circuit timing without affecting other LUTs, and recalculating timing metrics incrementally to optimize signal assignments and reduce propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static timing analysis tools are used to identify critical timing paths, then timing analysis is simplified, but false timing paths may be misidentified and timing objectives may not be met
Solution Approach 1:
The patent segments the timing analysis process into multiple phases: initial static timing analysis to identify potential critical paths, followed by incremental optimization phases that re-evaluate timing metrics after each LUT input swap. This segmentation allows the system to combine the simplicity of static analysis with the precision of iterative dynamic verification, reducing false positives while maintaining manageable complexity.
Solution Approach 2:
The patent performs preliminary static timing analysis to identify candidate critical timing paths before committing to full optimization. This preliminary action filters out obviously non-critical paths early, reducing the search space for subsequent incremental optimization phases and improving overall timing path identification accuracy without exhaustive analysis.
2Loss of time
If LUT input assignments are optimized for timing, then propagation delays are reduced, but the complexity of the optimization process increases
Solution Approach 1:
The patent implements dynamic optimization by iteratively swapping LUT input assignments and re-evaluating timing metrics after each change. Rather than performing a single complex global optimization, the system dynamically adjusts assignments in incremental steps, evaluating the impact of each swap on propagation delay. This dynamic approach reduces timing loss while keeping each optimization step manageable in complexity.
Solution Approach 2:
The patent applies partial optimization by focusing only on LUTs that lie on identified critical timing paths, rather than optimizing all LUTs in the design. This partial action concentrates optimization efforts where they have the greatest impact on propagation delay, reducing the overall complexity of the optimization process while achieving significant timing improvements.
3Measurement precision
If incremental timing recalculation is performed after each LUT optimization, then timing accuracy is improved, but computational overhead increases
Solution Approach 1:
The patent performs incremental timing recalculation only for the specific LUT and its associated timing paths that were modified, rather than recalculating timing metrics for the entire design. This partial recalculation maintains high timing metric accuracy for affected regions while significantly reducing computational energy consumption compared to full design re-analysis.
Solution Approach 2:
The patent applies local quality by focusing timing verification resources on the local region around modified LUTs. After each LUT input swap, the system performs detailed timing analysis only on the affected timing paths and neighboring LUTs, ensuring high measurement precision where it matters most while minimizing overall computational energy expenditure.
Data Source
AI summary
Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design implementation is determined. For each LUT in the subset at each topological level, a set combinations is determined for assigning signals to the inputs of the LUT. A current assignment of the signals to the LUT inputs is initialized according to the design implementation. For each LUT in the subset at each topological level, the method determines whether a respective assignment for each combination in the set for the LUT improves a timing metric for the LUT relative to the current assignment for the LUT, and the current assignment is updated when the respective assignment improves the timing metric for the LUT.