Reconfigurable LUT Linearization for Delay-Domain ADC Calibration
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Solution Overview
Problem
Delay domain ADC topologies suffer from nonlinearity, which is compensated by calibration using known inputs, but this process is affected by noise issues like DAC flicker noise, impacting accuracy.
Innovation Solution
A nonlinear ADC system with a linearization circuit and a reconfigurable lookup table (LUT) memory that stores initial, intermediate, and updated calibration data to correct nonlinearity, using iterative DAC ramps to determine and store updated calibration data, reducing noise-related errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If delay domain ADC topology is used, then power consumption and area are reduced, but nonlinearity increases
Solution Approach 1:
A linearization circuit is introduced as an intermediary component between the nonlinear delay domain ADC and the digital output. This circuit includes a reconfigurable LUT memory that stores calibration data and performs lookup operations to correct the nonlinear ADC output, thereby mediating the nonlinearity issue while preserving the power and area benefits of the delay domain topology
Solution Approach 2:
The LUT memory is made reconfigurable, allowing the calibration data to be updated and adjusted. This enables dynamic modification of the correction parameters to optimize linearity compensation while maintaining the low power consumption characteristics of the delay domain ADC
2Manufacturing precision
If calibration is performed using known inputs, then nonlinearity is compensated, but noise errors increase
Solution Approach 1:
The calibration process uses feedback from the nonlinear ADC output to update the LUT memory with corrected calibration data. The system performs calibration operations, stores the results in the reconfigurable LUT, and uses this feedback to continuously improve the linearity compensation while accounting for noise effects through iterative refinement
Solution Approach 2:
Calibration data is pre-computed and stored in the LUT memory before normal operation. The reconfigurable nature of the LUT allows preliminary calibration to be performed offline or during idle periods, separating the calibration process from the signal conversion process and reducing the impact of noise during actual measurements
3Manufacturing precision
If LUT memory is used for calibration, then nonlinearity is corrected, but area increases
Solution Approach 1:
The LUT memory is designed to serve multiple functions: storing calibration data for linearity correction, holding intermediate results during calibration operations, and potentially serving as buffer memory for other circuit operations. This multi-functionality reduces the need for dedicated separate memory components, thereby minimizing the overall area increase
Solution Approach 2:
The linearization circuit merges the LUT memory with the calibration control logic and the nonlinear ADC interface into an integrated structure. By combining these functions into a unified circuit block, the patent reduces the total area overhead compared to having separate independent components for each function
Data Source
AI summary
A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.