Multi-Output LUT Memory Cell for Lower-Cost FPGA Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high Non-Recurring Engineering (NRE) cost and complexity of designing and manufacturing Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips using advanced semiconductor technology nodes, which hinders innovation and increases barriers for implementing advanced technologies in semiconductor IC chips.
Innovation Solution
A standardized commodity logic drive in a multichip package comprising one or more standardized commodity FPGA IC chips, non-volatile memory IC chips, and cooperating or supporting IC chips, which allows for field programming and configuration, reducing the need for expensive ASIC or COT chip design and enabling innovation using advanced technology nodes at a lower cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ASIC or COT chip design is used to implement applications at advanced technology nodes, then manufacturing precision and performance are improved, but NRE cost and device complexity increase greatly
Solution Approach 1:
The patent employs a universal FPGA chip architecture that can be configured to perform multiple different application functions through reconfigurable logic blocks and interconnection structures. This single multi-functional platform replaces the need for multiple specialized ASIC designs, thereby reducing overall device complexity and NRE costs while maintaining manufacturing precision benefits from advanced technology nodes.
Solution Approach 2:
The patent implements dynamic reconfigurability in the FPGA architecture, allowing the logic blocks and interconnection structures to be programmatically adjusted after manufacturing. This dynamic adaptability enables the same physical hardware to optimize its configuration for different applications, achieving ASIC-level performance for specific tasks without incurring ASIC-level design complexity and cost.
2Productivity
If ASIC or COT chip design is used to implement applications at advanced technology nodes, then performance is improved, but NRE cost increases greatly
Solution Approach 1:
The universal FPGA platform provides a single chip design that can be reconfigured to achieve high performance across multiple different applications. By consolidating what would otherwise require multiple specialized ASIC designs into one reconfigurable platform, the patent reduces the cumulative NRE cost and device complexity while maintaining the ability to achieve ASIC-level performance for each specific application through optimized configuration.
3Adaptability or versatility
If FPGA design is used compared to ASIC or COT chip, then adaptability is improved, but manufacturing precision and fabrication yield worsen
Solution Approach 1:
The patent utilizes a universal FPGA architecture that maintains high adaptability through reconfigurable logic blocks while being manufactured using standardized processes at advanced technology nodes. This approach achieves manufacturing precision benefits from state-of-the-art fabrication while preserving FPGA-level adaptability, effectively decoupling the trade-off between customization capability and manufacturing quality.
4Adaptability or versatility
If FPGA design is used compared to ASIC or COT chip, then adaptability is improved, but power consumption and performance worsen
Solution Approach 1:
The patent implements dynamic reconfiguration capabilities in the FPGA architecture, allowing the system to optimize its power consumption by activating only the necessary logic blocks and interconnection structures for each specific application. This dynamic resource management reduces power consumption compared to traditional FPGAs while maintaining adaptability, and enables the system to achieve performance levels closer to specialized ASIC designs.
Data Source
AI summary
A semiconductor integrated-circuit (IC) chip comprises a memory cell including: a latch circuit comprising first and second inverters coupling to each other, a first latch node coupling to an input point of the first inverter and an output point of the second inverter and a second latch node coupling to an input point of the second inverter and an output point of the first inverter; a first N-type MOS transistor having a first terminal coupling to the first latch node, a second terminal coupling to a first output point of the memory cell, and a first gate terminal for controlling coupling between the first latch node and the first output point of the memory cell; a second N-type MOS transistor having a third terminal coupling to the second latch node, a fourth terminal coupling to a second output point of the memory cell, and a second gate terminal for controlling coupling between the second latch node and the second output point of the memory cell; and a P-type MOS transistor having a fifth terminal coupling to the first latch node, a sixth terminal coupling to a third output point of the memory cell, and a third gate terminal for controlling coupling between the first latch node and the third output point of the memory cell.