LUT-Based Processing-in-Memory Logic for High-Throughput Computing

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Solution Overview

Problem

Existing computer systems face challenges in improving throughput while avoiding exorbitant costs and energy consumption by increasing processing cores, particularly in applications requiring high degrees of parallelism.

Innovation Solution

Implementing reconfigurable processing-in-memory (PIM) logic using look-up tables (LUTs) in memory devices, which include logic arrays and control blocks to manage computations, enabling various computational pipelines such as superscalar, vector, and hardware neural networks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processing cores are increased to improve throughput, then computational performance is improved, but energy consumption and cost increase

Engineering Contradiction:
ImprovethroughputVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent combines memory storage and processing logic into a single integrated structure where logic arrays are directly coupled to memory cells. This merging eliminates the need for separate processing cores while enabling computations to be performed within the memory device itself, thereby improving throughput without proportionally increasing energy consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The logic arrays are designed to perform multiple computational functions including arithmetic operations, logical operations, and data movement. This multi-functionality allows a single integrated structure to replace multiple specialized processing cores, reducing overall system energy consumption while maintaining high throughput for various computational tasks.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If processing cores are increased to improve throughput, then computational performance is improved, but cost increases

Engineering Contradiction:
ImprovethroughputVSAvoidcost
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By merging memory and processing logic into an integrated PIM device, the patent eliminates the need for multiple separate processing cores and their associated interconnect structures. This consolidation reduces device complexity and manufacturing cost while maintaining high throughput through in-memory computation.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If specialized processors like ASICs, FPGAs, and GPUs are used for high parallelism applications, then computational performance is improved, but cost and energy consumption increase

Engineering Contradiction:
ImproveparallelismVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The PIM system performs computations directly within the memory device where data is stored, eliminating the need to transfer data between memory and separate processing units. This self-service approach enables high parallelism for memory-bound operations while significantly reducing the energy consumption associated with data movement and separate processing infrastructure.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260104895A1Reconfigurable processing-in-memory logic using look-up tables
Publication Date: 2026.04.16 LODESTAR LICENSING GROUP LLC
  • US20260104895A1 patent drawing
  • US20260104895A1 patent drawing
  • US20260104895A1 patent drawing

AI summary

An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data; a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data.