Logic Element LUT Register Configuration Without General Interconnect
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Solution Overview
Problem
Existing programmable logic devices (PLDs) lack local interconnect and hardware resources within logic elements to efficiently configure look-up tables (LUTs) as registers, leading to inefficient use of LUT resources and slow operational speed when used for pipelining.
Innovation Solution
Incorporating dedicated hardware within logic elements to configure LUTs as registers, utilizing cross-coupled muxes or latches, and providing dedicated interconnects to minimize propagation delays and enable efficient use of LUTs for both logic functions and pipelining.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LUTs are configured as registers using existing PLD architectures, then register functionality is achieved, but operational speed becomes too slow for practical use
Solution Approach 1:
The logic element is segmented into distinct functional components: LUTs for logic functions, dedicated registers for storage, and specialized interconnect structures. This segmentation allows LUTs to be efficiently configured as registers when needed while maintaining dedicated fast paths, resolving the speed limitation by separating the configuration flexibility from the execution path.
Solution Approach 2:
A dedicated interconnect structure acts as an intermediary between LUTs and registers, providing a specialized fast path for data transfer. This intermediary enables LUTs to operate as registers at high speeds by bypassing the general-purpose interconnect, thus resolving the speed contradiction while maintaining configurability.
2Productivity
If registers are used for pipelining to increase clock speed, then throughput improves, but LUT resources become wasted
Solution Approach 1:
LUTs are designed with multi-functionality, capable of operating either as logic function implementers or as registers for pipelining. The dedicated interconnect and control logic enable dynamic configuration, allowing the same LUT resource to serve dual purposes. This eliminates resource waste while maintaining throughput improvement from pipelining.
Solution Approach 2:
The logic element incorporates dynamic configuration capabilities, allowing LUTs to switch between logic function mode and register mode based on design requirements. This dynamic adaptability ensures optimal resource utilization while achieving the throughput benefits of pipelining, resolving the resource waste problem.
3Device complexity
If general interconnect is used for LUT-to-LUT signaling, then device complexity is reduced, but propagation delays increase
Solution Approach 1:
The interconnect structure implements local quality by providing specialized fast interconnect resources within logic elements for critical LUT-to-LUT signaling paths. While the overall device maintains a general-purpose interconnect for routing flexibility, local fast paths are introduced where speed is critical, resolving the propagation delay issue without significantly increasing overall device complexity.
Data Source
AI summary
A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.