Dual-Mode LUT6 Adder Slices for Low-Delay FPGA Addition
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) face challenges in efficiently implementing large adders due to sequential time delays, which hinder performance in applications like neural networks that require numerous additions, and existing designs often increase circuit complexity or require additional logic blocks.
Innovation Solution
The novel use of modified lookup tables (LUTs) that can operate in both traditional and adder modes, allowing for efficient packing of 2-bit adder slices within FPGAs without additional logic blocks, enabling the construction of arbitrarily sized adders with reduced complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 1-bit adders are chained to create larger adders, then the adder can perform addition of larger numbers, but the time delay increases proportionally with the number of bits
Solution Approach 1:
The patent pre-computes both possible sum outputs (one for carry-in=0 and one for carry-in=1) in parallel before the actual carry input is known. This preliminary computation of both possibilities eliminates the sequential waiting time, as the correct output can be immediately selected once the carry input arrives, rather than computing outputs sequentially.
Solution Approach 2:
The patent uses multiplexers to dynamically select between the two pre-computed sum outputs based on the actual carry input value. This dynamic selection mechanism allows the circuit to adapt its output based on the carry input without requiring sequential computation, thereby reducing time delay while maintaining adder versatility.
2Speed
If carry-select adder design is used to reduce time delays, then addition speed improves, but circuit complexity increases
Solution Approach 1:
The patent modifies LUTs to serve dual purposes: they function as both traditional logic lookup tables and as adder components. This multi-functionality allows the same hardware resources to perform both general logic operations and addition operations, reducing the need for dedicated adder circuits and thereby lowering overall circuit complexity while maintaining high addition speed.
Solution Approach 2:
The patent combines the LUT logic functionality with adder functionality into a unified structure. By merging these two functions into the same hardware blocks, the patent eliminates the need for separate adder circuits, reducing circuit complexity while preserving the speed benefits of carry-select adder architecture.
3Adaptability or versatility
If traditional LUTs are used for addition operations, then logic flexibility is maintained, but adder performance and efficiency are insufficient
Solution Approach 1:
The patent enhances LUTs to perform both traditional logic operations and addition operations with optimized performance. By making LUTs universal, the patent allows the same flexible logic blocks to deliver high-performance addition through their modified structure, which pre-computes both sum possibilities and uses multiplexers for rapid selection, thereby improving adder performance without sacrificing logic flexibility.
Data Source
AI summary
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.