LUT6 Adder Circuit for Faster FPGA Carry-Select Addition
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Solution Overview
Problem
Field-programmable gate arrays (FPGAs) face inefficiencies in implementing large adders due to sequential time delays, which hinder performance in applications like neural networks that require numerous additions, and existing designs complicate circuit complexity and power consumption.
Innovation Solution
The design introduces a novel LUT6 configuration that can operate as both a traditional LUT and a 2-bit adder, allowing for efficient packing of adder slices without additional logic blocks, enabling flexible configuration and reduced power consumption by minimizing the number of LUTs used for multiplication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential 1-bit adders are chained to create an N-bit adder, then the adder can be implemented with simple 1-bit logic blocks, but the time delay increases to N times the delay of a 1-bit adder
Solution Approach 1:
The patent pre-calculates and stores both possible sum outputs (one for carry-in=0 and one for carry-in=1) in lookup tables before the actual carry input is known. When the carry input becomes available, the corresponding pre-computed result is immediately selected, eliminating the sequential propagation delay through multiple 1-bit adder stages.
Solution Approach 2:
The patent creates parallel copies of the adder logic for both possible carry-in values (0 and 1). Instead of sequentially processing through N 1-bit adders, the system simultaneously computes both possible results and selects the correct one, effectively copying the computation path to eliminate sequential delays.
2Loss of time
If carry-select adder is used to reduce time delay by computing both possible outputs, then the addition speed improves, but the circuit complexity increases
Solution Approach 1:
The patent replaces the mechanical/circuit-based carry-select adder approach with a lookup table-based system. Instead of using complex combinatorial logic circuits to compute and select between two possible sums, the patent uses pre-computed tables stored in memory, substituting physical circuit complexity with data storage and retrieval operations.
Solution Approach 2:
The patent introduces lookup tables as an intermediary between the input operands and the final sum output. The LUTs act as a mediator that has already performed the complex computation of both possible sums, allowing the final stage to simply select the correct result based on the carry input, thereby reducing the complexity of the active computation path.
3Adaptability or versatility
If traditional LUT configurations are used for adder implementation, then the LUTs can perform general logic functions, but more LUTs are required for multiplication functions increasing power consumption
Solution Approach 1:
The patent designs LUTs that can serve multiple functions: they can be configured as traditional general-purpose logic LUTs or as specialized adder LUTs with pre-computed sum values. This multi-functionality allows the same hardware resource to adaptively serve different computational needs, reducing the overall number of LUTs required and thereby lowering power consumption.
Data Source
AI summary
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.