LVDC Data Formatting Circuit for Low-Power Noise-Resistant Bus Communication

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Solution Overview

Problem

Current data communication systems face challenges in efficiently transmitting and receiving digital data over a common bus while maintaining low power consumption and high noise immunity, especially in wireless communications where data errors are prevalent.

Innovation Solution

The implementation of Low Voltage Drive Circuits (LVDCs) that convert digital data into analog signals with a low magnitude oscillating component, allowing for low power, high noise immunity data transmission and reception, and enable multiple data streams to be transmitted on different frequencies, increasing data rate without significant power increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If digital data is transmitted using conventional high-voltage signaling, then noise immunity is improved, but power consumption increases

Engineering Contradiction:
Improvenoise immunityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the voltage parameter from conventional high-voltage digital signaling to low-voltage analog signaling with superimposed data. By transmitting data as voltage variations around a common-mode voltage level rather than full-rail digital swings, the system achieves both low power consumption and adequate noise immunity through differential signaling and controlled impedance matching.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple data streams are transmitted on different frequencies, then data rate is improved, but device complexity increases

Engineering Contradiction:
Improvedata rateVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs dynamic frequency assignment where LVDCs can be assigned to different frequencies on-demand rather than having fixed frequency allocations. This dynamic approach allows multiple data streams to share the same physical medium efficiently, increasing data rate while avoiding the complexity of dedicated hardware for each frequency channel.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The LVDC architecture provides universal functionality where a single circuit design can operate on multiple frequencies by receiving frequency assignment commands from a system controller. This multi-functionality allows the same hardware to handle different data streams at different frequencies, increasing productivity without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If low-voltage signaling is used, then power consumption is reduced, but noise immunity deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidnoise immunity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent introduces an intermediary approach by using a common-mode voltage level as a reference and transmitting data as small variations around this level. The receiver uses differential signaling and comparison against the common-mode reference to recover data, effectively filtering out common-mode noise while maintaining low voltage swings for power efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11294420B2Data formatting circuit of a low voltage drive circuit data communication system
Publication Date: 2022.04.05 SIGMASENSE LLC
  • US11294420B2 patent drawing
  • US11294420B2 patent drawing
  • US11294420B2 patent drawing

AI summary

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.