3D LVDMOS Transistor with Vertical Drain for Low On-Resistance
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Solution Overview
Problem
Conventional LDMOS transistors face challenges in achieving low on-resistance and high area efficiency, particularly in low power applications, due to the thin conduction path in top sections of vertically stacked configurations, leading to higher on-resistance and limited area savings.
Innovation Solution
A three-dimensional LVDMOS transistor structure is implemented with a drain structure vertically disposed underneath the gate and channel, incorporating a voltage attenuation structure in a lightly doped region of the semiconductor substrate, which reduces the drain side voltage and on-resistance, allowing for higher area efficiency and denser device arrangement without increasing lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertically stacked transistor configuration is used to improve area efficiency, then area savings are achieved, but on-resistance increases due to thin conduction path
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertically stacked configuration. The drain structure is positioned underneath the gate and channel, creating a vertical current path that significantly reduces the lateral area occupied by the device while maintaining effective conduction pathways through the substrate.
Solution Approach 2:
A lightly doped region is introduced as an intermediary structure between the heavily doped drain contact and the channel. This intermediate layer, positioned in the substrate underneath the gate, serves as a voltage attenuation structure that reduces the drain-side voltage and lowers on-resistance while enabling the vertical stacking architecture.
2Area of stationary object
If drain structure is vertically disposed underneath gate and channel, then area efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The device is segmented into distinct functional stacks: an upper stack containing the gate and channel structures, and a lower stack containing the drain structure and lightly doped region in the substrate. This segmentation allows each component to be optimized independently while simplifying the overall manufacturing process through modular fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly lowers on-resistance and maintains high breakdown voltage, achieving up to 60% area savings and reducing the drain side voltage from 5V to 1.5V, enabling more efficient and compact transistor designs compatible with CMOS technologies.
Implementation Method 1
a voltage attenuation structure in a lightly doped region of the semiconductor substrate, which reduces the drain side voltage
Data Source
AI summary
A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.