LVDS BIST Loopback for SoC Protocol Compatibility

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Solution Overview

Problem

Existing LVDS systems face compatibility issues between system-on-chips due to differing protocols, requiring costly silicon revisions to achieve interoperability.

Innovation Solution

Incorporation of a Built-In Self-Test (BIST) circuit within an LVDS system to determine valid communication parameter ranges, utilizing internal or external loopback paths to ensure compatibility with other SoCs, allowing flexible integration without silicon revisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different protocols are used by SoCs within the system, then device functionality and design flexibility are improved, but compatibility between SoCs deteriorates causing communication failure

Engineering Contradiction:
Improvedesign flexibilityVSAvoidcompatibility
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The BIST circuit dynamically adjusts communication parameters such as voltage levels, data rates, and timing characteristics to match the protocol requirements of different SoCs. By automatically modifying these parameters during testing, the system achieves compatibility across diverse devices without requiring fixed protocol configurations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The BIST circuit incorporates feedback mechanisms where test results from communication attempts are analyzed and used to adjust subsequent testing parameters. This closed-loop approach enables the system to learn from failed communications and adapt its testing strategy to achieve successful interoperability between different SoC protocols.

Inventive Principle:
Principle #23Feedback

2Reliability

If silicon revisions are performed to achieve compatibility, then communication reliability is improved, but manufacturing cost and development time increase

Engineering Contradiction:
Improvecommunication compatibilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The BIST circuit performs compatibility testing and parameter optimization during the manufacturing test phase rather than requiring post-production silicon revisions. By conducting comprehensive communication testing early in the manufacturing process and adjusting parameters accordingly, the system ensures compatibility is achieved before products reach customers, eliminating costly field revisions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The BIST circuit enables self-testing and self-adjustment of communication parameters within the SoC itself, eliminating the need for external testing equipment or manual silicon revisions. This self-service capability allows automatic detection and correction of compatibility issues during manufacturing, significantly reducing development costs and time.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If BIST circuit is implemented to determine valid parameter ranges, then compatibility flexibility is improved, but device complexity increases

Engineering Contradiction:
Improvecompatibility flexibilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The BIST circuit is designed to perform multiple functions including parameter sweeping, communication testing, result analysis, and automatic adjustment within a single integrated block. By consolidating these diverse functions into one universal circuit, the patent minimizes the additional complexity introduced while maximizing compatibility flexibility across different SoC protocols.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260067006A1Low voltage differential signaling (LVDS) system having a built-in self-testing (BIST) circuit
Publication Date: 2026.03.05 NXP USA INC
  • US20260067006A1 patent drawing
  • US20260067006A1 patent drawing
  • US20260067006A1 patent drawing

AI summary

A low voltage differential serial (LVDS) communication system includes a system-on-chip (SoC) which includes a transmitter configured to serially transmit data, a receiver configured to serially receive data, a loopback control circuit configured to provide transmitted test data from the transmitter directly to the receiver during testing, and a built-in self-test (BIST) circuit. The BIST circuit controls testing by setting a voltage level of a common mode voltage for the transmitter, providing a test data pattern for transmission by the transmitter and receiving the test data pattern from the receiver in which the loopback control circuit directly provides the transmitted test data pattern from the transmitter to the receiver when an internal loopback configuration is enabled, and determining whether the voltage level of the common mode voltage results in a pass or fail.