Low-Voltage Differential Signaling Driver Circuit Topology

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Solution Overview

Problem

Low-voltage differential signaling (LVDS) driving circuits require high output currents and voltages to drive receivers, leading to increased power consumption and larger component sizes, which in turn increase load and power noise in front-end circuits.

Innovation Solution

The LVDS driving circuit employs a voltage-driven design with resistors in series connection with the load resistor, reducing the output current and power consumption by using a lower voltage, allowing for smaller MOS switch sizes and reduced load on the front-end circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage (2.5V or 3.3V) and large current are used to drive the receiver, then the transmission effect is improved, but power consumption increases

Engineering Contradiction:
Improvetransmission effectVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the voltage parameter from conventional high voltage (2.5V or 3.3V) to low voltage (1.2V), and simultaneously changes the resistor connection configuration from parallel to series, thereby reducing power consumption while maintaining transmission effectiveness

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent inverts the conventional parallel connection of resistors to a series connection, which fundamentally changes the current path and voltage distribution, enabling low-voltage operation while maintaining the required transmission signal levels

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If high voltage is used, then the transmission effect is improved, but the MOS switch size increases

Engineering Contradiction:
Improvetransmission effectVSAvoidMOS switch size
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent changes the operating voltage parameter from high voltage to low voltage (1.2V), which directly enables the use of smaller MOS switch sizes while maintaining adequate transmission performance

Inventive Principle:
Principle #35Parameter changes

3Strength

If large-sized components are used, then the voltage withstanding capability is improved, but the load on front-end circuit increases

Engineering Contradiction:
Improvevoltage withstanding capabilityVSAvoidload on front-end circuit
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent changes the voltage parameter to low voltage (1.2V), which eliminates the need for large-sized components with high voltage withstanding capability, thereby reducing the load on front-end circuits

Inventive Principle:
Principle #35Parameter changes

4Strength

If large-sized components are used, then the voltage withstanding capability is improved, but power noise increases

Engineering Contradiction:
Improvevoltage withstanding capabilityVSAvoidpower noise
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The patent changes the operating voltage to low voltage (1.2V), which enables the use of smaller components that generate less power noise, while still maintaining adequate voltage withstanding capability for the application

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10209723B2Low-voltage differential signaling driving circuit
Publication Date: 2019.02.19 MEDIATEK INC
  • US10209723B2 patent drawing
  • US10209723B2 patent drawing
  • US10209723B2 patent drawing

AI summary

A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.