LVDS BIST Loopback for Common-Mode Compatibility Mapping
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Solution Overview
Problem
Existing LVDS systems face compatibility issues when different system-on-chips (SoCs) have incompatible protocols, leading to communication failures and costly silicon revisions.
Innovation Solution
A built-in self-testing (BIST) circuit within an SoC determines valid communication parameter ranges, such as common mode voltage (Vcm), using internal or external loopback paths to ensure compatibility with other SoCs without requiring silicon revisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different SoCs use different communication protocols, then each SoC can be optimized for specific functions, but compatibility between SoCs is lost and communication fails
Solution Approach 1:
The BIST circuit automatically adjusts communication parameters such as common mode voltage (Vcm) levels, differential voltage swings, and timing characteristics to match the requirements of different SoC protocols. By dynamically changing these electrical parameters, the system achieves compatibility across multiple protocol standards without requiring hardware revisions.
Solution Approach 2:
The BIST circuit performs self-testing and self-configuring functions by automatically generating test patterns, measuring communication parameter ranges, and determining optimal settings without external intervention. This self-service capability enables the system to adapt to different SoC protocols autonomously, ensuring compatibility while maintaining protocol-specific optimizations.
2Reliability
If silicon is revised or redesigned to achieve compatibility between SoCs, then communication compatibility is improved, but development cost and time increase
Solution Approach 1:
The BIST circuit is pre-integrated into the SoC design to perform automatic parameter measurement and validation before final product deployment. By conducting compatibility testing and parameter optimization in advance during the BIST phase, the system identifies and resolves compatibility issues early, eliminating the need for costly post-manufacturing silicon revisions.
Solution Approach 2:
The BIST circuit continuously monitors communication parameters and provides feedback on compatibility status. This feedback mechanism allows developers to identify compatibility issues early in the design process and make software or configuration adjustments rather than requiring expensive silicon redesigns and remanufacturing.
3Adaptability or versatility
If communication parameters are not properly set, then system integration is simplified, but compatibility between devices with different protocols fails
Solution Approach 1:
The BIST circuit automatically performs parameter measurement, validation, and optimization without requiring manual configuration. The system self-determines the valid parameter ranges for different protocols and automatically configures the communication interface, eliminating the need for complex manual parameter setting while achieving broad protocol compatibility.
Solution Approach 2:
The BIST circuit systematically varies communication parameters such as common mode voltage, differential swing, and timing values to map out valid operating ranges for different protocols. By automatically exploring and identifying optimal parameter settings, the system achieves protocol compatibility without requiring complex manual configuration procedures.
Data Source
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AI summary
A low voltage differential serial (LVDS) communication system includes a system-on-chip (SoC) which includes a transmitter configured to serially transmit data, a receiver configured to serially receive data, a loopback control circuit configured to provide transmitted test data from the transmitter directly to the receiver during testing, and a built-in self-test (BIST) circuit. The BIST circuit controls testing by setting a voltage level of a common mode voltage for the transmitter, providing a test data pattern for transmission by the transmitter and receiving the test data pattern from the receiver in which the loopback control circuit directly provides the transmitted test data pattern from the transmitter to the receiver when an internal loopback configuration is enabled, and determining whether the voltage level of the common mode voltage results in a pass or fail.