LVDS Output Driver with Pre-emphasis and Feedback Control
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Solution Overview
Problem
Existing LVDS output drivers face challenges in maintaining a stable common mode voltage due to manufacturing variations in resistors, which affects the amplitude of differential signals, and struggle to support high-definition image requirements with faster data communication needs.
Innovation Solution
The output driver incorporates a differential signaling circuit with a bias current generation mechanism, a differential voltage circuit, and pre-emphasis circuit to control the bias current based on differential voltage, ensuring high slew rates and stable differential signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the common mode voltage is generated based on the voltage generated in a resistor provided as a replica of a terminating resistor of the LVDS driver, then the amplitude of the output differential signal fluctuates due to manufacturing variations in the resistor
Solution Approach 1:
The patent implements a feedback mechanism where the common mode voltage is continuously monitored and adjusted. The output driver includes a common mode voltage generation circuit that receives feedback about the actual common mode voltage level and modifies the bias current accordingly to maintain the desired voltage level, thereby compensating for resistor manufacturing variations
Solution Approach 2:
The patent changes the parameter being controlled from direct voltage generation to bias current control. By controlling the bias current flowing through the differential signaling circuit based on feedback, the system can compensate for resistor variations without being directly dependent on precise resistor values
2Speed
If the bias current is increased to achieve faster data communication for high-definition images, then the slew rate improves, but the common mode voltage becomes less stable due to manufacturing variations
Solution Approach 1:
The feedback mechanism continuously monitors the common mode voltage and adjusts the bias current to maintain stability. This allows the system to operate at higher speeds while automatically compensating for any drift in common mode voltage caused by high current operation or manufacturing variations
Solution Approach 2:
The system transitions from a static bias current approach to a dynamic control mechanism. The bias current is continuously adjusted based on feedback conditions, allowing the system to adapt to changing operating conditions and maintain stability across different speed requirements
3Device complexity
If a conventional LVDS driver is used to maintain common mode voltage, then the circuit complexity is low, but the slew rate is insufficient for high-definition image requirements
Solution Approach 1:
The patent implements pre-emphasis functionality that prepares and boosts the signal before it is transmitted. The pre-emphasis circuit adds a leading edge to the differential signal, effectively increasing the slew rate without requiring a complete redesign of the entire driver architecture
Solution Approach 2:
The patent combines multiple functions into a unified output driver architecture. The differential signaling circuit, common mode voltage generation circuit, and pre-emphasis circuit are integrated to work together, achieving high slew rate performance while maintaining reasonable circuit complexity through shared components and coordinated operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the slew rate of the output driver, allowing it to maintain a stable common mode voltage and support faster data communication, effectively addressing the limitations of existing LVDS drivers.
Implementation Method 1
a first transistor that generates a bias current
Implementation Method 2
a resistor circuit connected between the first node and second node, and outputs voltages generated respectively at the first node and the second node
Implementation Method 3
a first operational amplifier that takes a voltage generated at the other end of the first resistor as a first center voltage indicating a center voltage of the pair of differential clock signals
Implementation Method 4
a first pre-emphasis circuit that executes a pre-emphasis processing in response to changes in a level of the clock signal, generating a current based on the first differential voltage and adding it to the first bias current
Data Source
AI summary
An output driver according to the disclosure includes a differential signaling circuit that includes a first transistor that generates a bias current, first and second nodes, and a resistor circuit connected between the first and second nodes, and outputs voltages respectively at the first and second nodes as a pair of differential signals by supplying the bias current to one of the first and second nodes based on a level of the input signals, a differential voltage circuit that supplies a differential voltage representing a difference between a center voltage of voltages between the first node and the second node and a predetermined reference voltage to a gate of the first transistor; and a pre-emphasis circuit that executes a pre-emphasis processing in response to changes in the level of the input signal, generating a current based on the differential voltage and adding it to the bias current.