LVDS Receiver Input Stage for Wide Common-Mode Range at Low Current
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Solution Overview
Problem
Existing low-voltage differential signaling (LVDS) receiver circuits consume high power and current due to the use of complementary NMOS and PMOS differential pairs, which limits their efficiency in achieving a wide range of input common mode voltages.
Innovation Solution
The implementation of a single NMOS differential transistor pair with source follower or level shifter stages allows the LVDS receiver to operate with a wide range of input common mode voltages, utilizing NMOS transistors for higher voltages and level shifters for lower voltages, thereby reducing power consumption and current usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complementary NMOS and PMOS differential pairs are used to achieve wide range input common mode voltages, then the input voltage range is improved, but power consumption and current usage increase
Solution Approach 1:
The patent extracts the PMOS differential pair from the traditional complementary input stage, retaining only the NMOS differential pair. This removal eliminates the high current consumption associated with PMOS devices while preserving the essential differential signaling function through the NMOS pair and level shifter combination.
Solution Approach 2:
The level shifter circuit acts as an intermediary component that enables the NMOS differential pair to handle lower input common mode voltages. By introducing this intermediate stage, the circuit achieves wide input voltage range coverage without requiring the high-current PMOS differential pair.
2Adaptability or versatility
If complementary NMOS and PMOS differential pairs are used to achieve wide range input common mode voltages, then the input voltage range is improved, but current consumption increases
Solution Approach 1:
The patent extracts the PMOS differential pair from the traditional complementary input stage, retaining only the NMOS differential pair. This removal eliminates the high current consumption associated with PMOS devices while preserving the essential differential signaling function through the NMOS pair and level shifter combination.
Solution Approach 2:
The patent changes the operating parameters of the input stage by using NMOS transistors with optimized sizing and biasing conditions. The level shifter circuit modifies the voltage levels to enable the NMOS pair to operate effectively across a wide input common mode range with lower current consumption.
3Adaptability or versatility
If simple input stages are used to meet rail-to-rail common mode input range specification, then the input voltage range is improved, but device complexity increases
Solution Approach 1:
The patent segments the input stage into two functional parts: the NMOS differential pair for handling higher input voltages and the level shifter circuit for handling lower input voltages. This segmentation allows each component to be optimized for its specific voltage range, achieving wide input range coverage without requiring a complex complementary structure.
Solution Approach 2:
The level shifter circuit serves multiple functions: it extends the input voltage range downward, provides proper biasing for the NMOS differential pair, and enables the circuit to handle rail-to-rail input voltages. This multi-functionality reduces the need for additional dedicated components.
Data Source
AI summary
Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.