LVDS Receiver Input Stages for Rail-to-Rail Noise Immunity

The input buffer is divided into two separate input stages: a first input stage with a first transistor pair and a second input stage with a second transistor pair. Each stage processes a portion of the input voltage range, allowing the receiver to handle the full rail-to-rail range while each individual stage operates within a narrower, less noisy range. This segmentation resolves the contradiction by enabling wide voltage range operation without exposing any single stage to the full extent of common-mode noise.

Different transistor pairs are used in different input stages, with each transistor pair optimized for specific operating conditions within the voltage range. The first transistor pair handles lower voltage portions while the second transistor pair handles higher voltage portions, allowing each component to operate in its optimal performance region and reducing susceptibility to common-mode noise in each local operating region.

The receiver's input buffer is segmented into multiple input stages, each handling a specific portion of the rail-to-rail voltage range. This allows the system to achieve wide voltage range adaptability while each individual stage maintains reliable operation with reduced noise susceptibility within its designated operating range.

The patent introduces intermediate circuitry between the differential input signals and the output, including multiple transistor pairs and current mirrors that act as intermediaries. These intermediate stages process and condition the signals progressively, allowing the system to handle rail-to-rail voltages while maintaining signal integrity and immunity to common-mode noise through controlled signal transformation at each intermediate stage.

Multiple input stages with different transistor pairs are merged into a single unified input buffer structure that processes differential signals together. The current mirrors and load circuits are shared between stages, allowing the system to achieve rail-to-rail operation with reduced overall complexity compared to implementing separate independent circuits for each voltage range.

The input buffer is designed as a universal circuit that can handle the entire rail-to-rail input voltage range through its multiple transistor pairs. Each transistor pair and associated current mirror serves multiple functions: signal amplification, voltage level shifting, and noise filtering, allowing the circuit to achieve wide voltage range operation without proportionally increasing complexity.