LVDS Receiver Input Stage for Rail-to-Rail Voltage Range
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Achieving a rail-to-rail input voltage range in LVDS receivers is challenging due to susceptibility to common-mode noise and interference, limiting the usable input voltage range.
Innovation Solution
The LVDS receiver design incorporates a resistor load pair, input stage with P-type and N-type transistor pairs, current mode logic stage, and latch circuit to generate and enhance differential output voltages, and a comparator circuit to convert to a single-ended output signal, enabling operation across a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional LVDS receiver design is used, then the circuit structure is simple, but the input voltage range is limited due to susceptibility to common-mode noise
Solution Approach 1:
The input buffer is divided into two separate input stages: a first input stage with a first transistor pair (PMOS) for generating first differential output voltages, and a second input stage with a second transistor pair (NMOS) for generating second differential output voltages. Each stage handles different voltage ranges, allowing the receiver to achieve rail-to-rail input voltage range while maintaining manageable circuit complexity through modular design.
2Adaptability or versatility
If the LVDS receiver operates across a wide voltage range, then the adaptability is improved, but the power consumption increases
Solution Approach 1:
The patent applies different transistor types with different characteristics to different parts of the circuit: PMOS transistors in the first input stage are optimized for certain voltage ranges, while NMOS transistors in the second input stage are optimized for other voltage ranges. This local differentiation allows each stage to operate efficiently in its optimal voltage range, achieving wide voltage coverage without proportionally increasing power consumption.
Solution Approach 2:
The circuit dynamically switches between the first and second input stages depending on the input voltage range. The first input stage handles lower voltage ranges while the second input stage handles higher voltage ranges, allowing the receiver to adapt its operating characteristics to match the input conditions and maintain low power consumption across the entire voltage range.
3Speed
If a single transistor pair is used in the input stage, then the device complexity is low, but the response time is slow
Solution Approach 1:
The input stage is segmented into two parallel paths: the first input stage with PMOS transistors for fast response in lower voltage ranges, and the second input stage with NMOS transistors for fast response in higher voltage ranges. This segmentation allows the circuit to achieve fast response times across the entire voltage range by selecting the appropriate path based on input conditions.
Solution Approach 2:
The patent merges the outputs of the first and second input stages through a latch circuit that combines the first differential output voltages and second differential output voltages. This merging allows the circuit to leverage the fast response characteristics of both PMOS and NMOS transistor pairs, achieving overall fast response time while handling the complexity through integrated output combination.
Data Source
AI summary
A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.