LVDS Interface Timing Training for Glitch-Free Sampling Alignment
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Solution Overview
Problem
Existing timing training methods for LVDS interfaces in FPGAs face challenges with glitches in data streams due to delay chain stage switching, inability to handle chip OCV variations, and the impact of asymmetry between the rise and fall slopes of LVDS signals on window accuracy.
Innovation Solution
A method involving inputting LVDS differential data signals into separate delay chains for parallel conversion, sampling, and adjusting delay stages to center the sampling position within the data window, thereby calculating and setting the optimal delay stage to minimize stage differences and asymmetry effects, ensuring accurate timing training without introducing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the stage count of the delay chain is changed to adjust phase, then the timing relationship between serial data and sampling clock is improved, but glitches are introduced in the data stream
Solution Approach 1:
The patent performs timing training before normal data transmission by sending training sequences. This preliminary action allows the system to determine the optimal sampling position and configure the delay chain stage count in advance, so that when normal operation begins, the delay chain is already set to the correct stage and no further switching is needed, thus avoiding glitches in the data stream.
Solution Approach 2:
The patent uses periodic training sequences to calibrate the timing relationship. By transmitting known training patterns at regular intervals or during initialization, the system can periodically re-synchronize and adjust the delay chain stages, ensuring accurate timing without requiring continuous stage switching during normal data transmission.
2Measurement precision
If training sequences are sent for interface timing training, then timing accuracy is improved, but transmission time is increased
Solution Approach 1:
The patent sends training sequences only partially - specifically during initialization or periodic calibration intervals - rather than continuously. This partial application of training allows the system to achieve sufficient timing accuracy without the excessive time loss that would result from continuous training sequence transmission.
3Device complexity
If existing timing training methods are used, then implementation simplicity is maintained, but window accuracy is degraded due to OCV variations
Solution Approach 1:
The patent implements a feedback mechanism where the receiver compares the received training sequence with the expected sequence, determines the sampling position accuracy, and uses this information to adjust the delay chain stage count. This feedback loop continuously optimizes the timing alignment, compensating for OCV variations and improving window accuracy while maintaining reasonable implementation complexity through automated adjustment.
4Length of stationary object
If delay chains are cascaded to achieve required delay, then delay range is increased, but delay differences due to OCV are amplified
Solution Approach 1:
The patent changes the operational parameters of the delay chain by dynamically adjusting the stage count based on feedback from timing training. By optimizing the delay configuration to match actual operating conditions and compensating for OCV effects through calibration, the system achieves the required delay range while minimizing the impact of delay variations caused by manufacturing tolerances.
Data Source
AI summary
A method and apparatus for timing training on an LVDS interface includes sampling by using the second parallel data as reference data and the first parallel data as scanning data, the first delay stage is obtained; sampling by using the first parallel data as reference data and the second parallel data as scanning data, and setting the initial delay stage of the second parallel data as the first delay stage, the second delay stage is obtained, and setting the sum of the first delay stage and half of the delay stage difference as the delay stage of the first parallel data, then receiving the LVDS differential data. The method is capable of handling the impact of OCV and asymmetry in signal slopes on the effective data window, avoiding glitches, and reducing the requirements for delay chain design.