LVDS Transmitter Clocking With Single-PLL Phase Synchronization
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Solution Overview
Problem
In LVDS interfaces, particularly in vehicular devices, the use of two phase-locked loops leads to poor synchronization between clock and data signals due to different signal paths, resulting in phase differences and limited clock following capability, especially in dual-link transmission.
Innovation Solution
A low voltage differential signal transmitter comprising a controller and a physical layer chip, where the controller processes a received clock signal to generate a second clock signal, allowing the physical layer chip to sample and output synchronized serial low voltage differential clock and data signals, utilizing a single phase-locked loop to ensure phase alignment within a preset range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two phase locked loops are used to generate clock signals for LVDS interface, then clock signal generation capability is improved, but synchronization between clock and data signals deteriorates due to different signal paths
Solution Approach 1:
The patent merges the clock signal generation function into a single external PLL, eliminating the internal PLL from the Phy chip. This consolidation ensures that both clock and data signals originate from the same timing source, thereby maintaining synchronization while preserving clock signal generation capability.
Solution Approach 2:
The controller acts as an intermediary between the external PLL and the Phy chip. It receives the pixel clock from the external PLL, processes it to generate the sampling clock, and coordinates data reading accordingly. This intermediary role ensures that clock and data signals remain synchronized through a unified timing path.
2Speed
If two phase locked loops are used in the LVDS interface, then clock signal generation is improved, but device complexity increases
Solution Approach 1:
The patent extracts the PLL function from the Phy chip and places it in an external device. This removes the complex internal PLL circuitry from the Phy chip, reducing device complexity while maintaining the necessary clock signal generation capability through the external PLL.
Solution Approach 2:
The external PLL serves multiple functions: generating the pixel clock for the controller and providing the sampling clock reference for the Phy chip. This multi-functional approach eliminates the need for separate PLLs in both the controller and Phy chip, thereby reducing overall system complexity.
3Speed
If two phase locked loops are used for clock signal generation, then clock frequency requirements are met, but power consumption increases
Solution Approach 1:
By extracting the PLL function to an external device, the patent eliminates redundant power consumption associated with maintaining two separate PLLs. The external PLL generates both the pixel clock and sampling clock reference, reducing overall power consumption while meeting all clock frequency requirements.
4Speed
If internal PLL changes duty cycle of pixel clock signal to 4/7, then sampling clock frequency is adjusted, but phase difference between clock and data signals occurs
Solution Approach 1:
The patent merges the sampling clock generation into the controller's timing logic rather than using a separate internal PLL in the Phy chip. The controller generates the sampling clock based on the external PLL's pixel clock, ensuring that both clock and data signals are derived from the same timing reference, thereby eliminating phase alignment issues.
Data Source
AI summary
The present disclosure discloses a low voltage differential signal transmitter, a method for generating a low voltage differential signal, and a data transmission device, the low voltage differential signal transmitter includes a controller and a physical layer chip connected with each other, the controller is configured to receive a first clock signal, process the first clock signal to obtain a second clock signal, read a first data signal under drive of the second clock signal, and output a third clock signal and a second data signal; the physical layer chip is configured to receive the first clock signal and the signals output by the controller, sample the third clock signal and the second data signal according to the first clock signal, and output a serial low voltage differential clock signal and a serial low voltage differential data signal.