LVS Verification Using DRC Syntax for IC Connectivity
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Solution Overview
Problem
Conventional Layout-Versus-Schematic (LVS) verification tools face challenges in efficiently verifying connectivity patterns in miniaturized semiconductor devices, leading to slow operation, high error rates, and increased complexity due to the vast amount of connectivity information required.
Innovation Solution
A method that automatically detects connectivity between polygons in integrated circuit (IC) layout data using a rule file with Design Rule Check (DRC) syntax, extracts a layout netlist, and performs LVS verification by comparing it with schematic data, reducing data size and eliminating the need for manual connectivity description.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional LVS verification methods are used to verify connectivity patterns in miniaturized semiconductor devices, then verification completeness is maintained, but operation speed decreases and error rates increase
Solution Approach 1:
The patent extracts and utilizes DRC syntax rules from the rule file to automatically detect connectivity patterns between polygons. By taking out the connectivity detection function and implementing it through DRC-based polygon interaction analysis, the system achieves faster verification speed while maintaining reliability through systematic rule-based detection
Solution Approach 2:
The LVS verification system performs self-service by automatically detecting connectivity through DRC syntax without requiring manual connectivity description. The system uses its own DRC rule file to autonomously identify polygon connections, extract layout netlists, and complete verification, thereby improving speed while maintaining accuracy through consistent rule application
2Productivity
If manual connectivity description is used in LVS verification, then connectivity information is captured, but design time increases and complexity increases
Solution Approach 1:
The DRC rule file serves multiple functions: it defines manufacturing design rules and simultaneously provides connectivity detection logic through polygon interaction syntax. This multi-functionality eliminates the need for separate manual connectivity description, improving productivity while reducing process complexity through unified rule-based handling
Solution Approach 2:
The system automatically generates connectivity information by performing DRC analysis on layout polygons using the rule file syntax. This self-service approach eliminates manual connectivity description, thereby improving design efficiency while reducing verification process complexity through automated rule-based detection
3Measurement precision
If connectivity patterns are detected using DRC syntax, then verification speed improves and errors are reduced, but data processing complexity increases
Solution Approach 1:
The patent merges DRC rule checking with connectivity detection functionality. By combining these functions and utilizing polygon interaction syntax within the existing DRC framework, the system achieves precise connectivity detection without introducing separate complex processing systems, thereby maintaining measurement precision while managing data processing complexity through integration
Data Source
AI summary
A method of manufacturing an IC includes detecting connectivity between polygons from layout data of the IC and extracting a layout netlist, by performing a DRC on the layout data. The DRC includes loading a rule file including a DRC syntax. The method includes performing LVS verification on the extracted layout netlist and schematic data of the IC to generate LVS result data. The method includes manufacturing the IC according to a layout based on the layout data and the LVS result data.