M-ary Symbol Storage Device With L-Patterned Pulse Width
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Solution Overview
Problem
Current storage devices face challenges in increasing information writing density while maintaining signal quality, as higher writing densities lead to inter-symbol interference and deteriorated reproduction signal quality, especially when trying to achieve multi-level writing without multiple sub-tracks.
Innovation Solution
The storage device converts user data into M-ary symbols and records them as signals with L-patterned pulse width, allowing for multi-level writing without multiple sub-tracks, using a controller circuit with conversion and equalization functions to manage pulse width modulation and demodulation, thereby enhancing writing density and signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If binary writing is used in storage devices, then the writing process is simple and reliable, but the linear writing density is low and data storage per unit area is limited
Solution Approach 1:
The patent changes the fundamental parameter of data representation from binary (2 levels) to M-ary (multiple levels). By encoding data as M-ary symbols where each symbol can take one of M different values, the system achieves multi-level writing without increasing physical track complexity. This parameter change directly increases linear writing density while maintaining manageable process complexity through systematic encoding schemes.
Solution Approach 2:
The patent introduces a new dimension in signal representation by using pulse width modulation with L-patterned widths. Instead of only varying signal amplitude or frequency, the system modulates the temporal dimension (pulse width) to encode additional information. This dimensional expansion allows multiple data levels to be represented within the same physical track, increasing storage density without proportionally increasing device complexity.
2Quantity of substance
If multi-level writing is attempted without multiple sub-tracks, then storage density increases, but inter-symbol interference occurs and reproduction signal quality deteriorates
Solution Approach 1:
The patent incorporates feedback mechanisms through equalization circuits that detect and correct inter-symbol interference in real-time. The system monitors the reproduction signal quality and adjusts the equalization parameters to compensate for distortion caused by multi-level writing. This feedback loop maintains signal reliability despite the increased density and potential interference, allowing high storage capacity without sacrificing read accuracy.
Solution Approach 2:
The patent applies preliminary equalization and signal conditioning before the actual reading process. By pre-compensating for expected inter-symbol interference through carefully designed pulse patterns and equalization filters, the system prevents signal degradation before it occurs. This preliminary action ensures that even with tight spacing and multi-level encoding, the reproduced signals remain clear and error-free.
3Quantity of substance
If higher writing density is achieved, then more data is stored per unit area, but inter-symbol interference increases and signal quality deteriorates
Solution Approach 1:
The patent converts the harmful effect of inter-symbol interference into a beneficial feature by using controlled pulse width patterns. Instead of trying to completely eliminate pulse overlap, the system designs L-patterned pulse widths where the interference patterns are predictable and can be systematically decoded. The overlapping pulses, which would normally be harmful, become part of the encoding scheme itself, allowing higher density while maintaining signal integrity through the structured interference pattern.
Data Source
AI summary
According to one embodiment, there is provided a storage device including a controller circuit and a storage medium. The controller circuit includes a first conversion circuit and a second conversion circuit. The first conversion circuit converts data into M-ary symbols where M is an integer of 3 or more. The second conversion circuit converts respective ones of the converted n samples of M-ary symbols into signals with L-patterned pulse width where n is an integer of 2 or more. The storage medium stores the converted n samples of signals with L-patterned pulse width. The controller circuit further includes an equalization circuit that equalizes signals read from the storage medium into the n samples of M-ary symbols.