M-Level Clock Recovery Using One Sample Per Symbol

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Solution Overview

Problem

Current clock recovery methods in high-speed optical transmission systems face challenges with oversampling and high jitter, especially at high data speeds, and require either expensive components or complex digital signal processing, making them unsuitable for low-power, small-size transceivers.

Innovation Solution

A novel clock recovery apparatus and method using a single sample per symbol, employing an M-level log2(M)-bit analog-to-digital converter and a logic unit with a truth table to compare amplitude differences between samples, allowing for digital output signal generation without analog processing, suitable for PAM-4 or PAM-8 systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional clock recovery methods are used in high-speed optical transmission systems, then clock extraction can be achieved, but oversampling and high jitter occur, and expensive components or complex DSP are required

Engineering Contradiction:
Improveclock extraction accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the sampling parameter from multiple samples per symbol to exactly one sample per symbol. This parameter change simplifies the system by eliminating oversampling while maintaining clock extraction accuracy through a specially designed truth table that processes the single sample effectively

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts only the essential information needed for clock recovery from the received signal by using a truth table that processes a single sample per symbol. This extraction approach eliminates unnecessary oversampling and complex processing, reducing system complexity while maintaining functionality

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If advanced modulation formats with DSP are used to support 100-G applications, then transmission capacity increases, but expensive components and enhanced DSP are required

Engineering Contradiction:
Improvetransmission capacityVSAvoidcomponent cost and DSP complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces expensive high-bandwidth optics and electronics with a simpler, cheaper solution using PAM-4 modulation and a simplified clock recovery apparatus. The system uses standard components with adequate bandwidth rather than expensive high-performance components, making 100-G applications economically viable

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the modulation format parameter from OOK to PAM-4, which doubles the spectral efficiency. Combined with the one-sample-per-symbol clock recovery method, this enables higher transmission capacity using cheaper, lower-bandwidth components

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If PAM-4 format is used with simple analog equalization, then transceiver cost decreases, but clock recovery requires two samples per symbol increasing complexity

Engineering Contradiction:
Improvetransceiver costVSAvoidclock recovery complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

Instead of using two samples per symbol as in conventional approaches, the patent inverts the approach by using exactly one sample per symbol. The truth table is specifically designed to extract clock information from this single sample, simplifying the clock recovery apparatus while maintaining effectiveness

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables clock extraction at very high Baud rates with simplified implementation, reducing sampling speed and eliminating the need for enhanced DSP, making it suitable for small-size and low-power transceivers, while maintaining reliable bit error rates.

Implementation Method 1

an M-level log 2 (M)-bit analog-to-digital converter adapted to convert a first analog data (x1) of the M-level signal to a digital data

Methodology Applied
Scientific EffectAnalog-to-digital conversion:

Implementation Method 2

a first comparator adapted to compare an amplitude difference between the first analog data (x1) and a second analog data (x2)

Methodology Applied
Scientific EffectAmplitude comparison:

Data Source

PatentEP3440813B1Apparatus and method for recovering clock data from an m-level signal
Publication Date: 2021.01.13 HUAWEI TECH CO LTD
  • EP3440813B1 patent drawingFigure 1~2
  • EP3440813B1 patent drawingFigure 3~4
  • EP3440813B1 patent drawingFigure 5~6

AI summary

The present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system, wherein a first analog data (x1) of the M-level signal is converted to a digital data, an amplitude difference between the first analog data (x1) and a second analog data (x2) is compared, and a digital output signal is provided through a truth table based on the digital data and the result of comparison of the amplitude difference, wherein the first analog data (x1) and the second analog data (x2) are sampled at a distance of one symbol period with respect to each of the first analog data (x1) and the second analog data (x2), and the first analog data (x1) and the second analog data (x2) have an identical polarity.