M-Sequence Generator Feedback Multiplication for Natural Noise-Like Errors
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Solution Overview
Problem
Conventional M-sequence generators produce pseudo-random numbers with probability distributions that significantly differ from naturally generated noise, leading to inadequate error distribution in communication systems, and have limitations in circuit scale and high-speed operation due to the use of primitive polynomials with a small number of terms.
Innovation Solution
An M-sequence generator with a Galois field multiplying unit that employs primitive polynomials with a large number of terms, allowing for increased bit data feedback and randomized error distribution, and the use of specified power values for Galois field multiplication to enhance randomness, while maintaining a maximum length period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If primitive polynomials with a small number of terms are used in the M-sequence generator, then the circuit scale is reduced and high-speed operation is enabled, but the probability distribution of the generated pseudo-random numbers significantly differs from naturally generated noise, resulting in inadequate error distribution
Solution Approach 1:
The patent changes the parameter of the primitive polynomial from having a small number of terms to having a large number of terms. Specifically, it uses primitive polynomials with 5 or more terms (such as pentanomials or higher) instead of traditional trinomials or quadrinomials. This parameter change increases the number of feedback taps in the linear feedback shift register, which improves the probability distribution characteristic of the generated pseudo-random sequence to better approximate naturally generated noise, while still maintaining circuit feasibility and operation speed.
2Reliability
If primitive polynomials with a large number of terms are used in the M-sequence generator, then the probability distribution characteristic approximates naturally generated noise, but the circuit scale increases and high-speed operation becomes difficult
Solution Approach 1:
The patent segments the feedback structure by using multiple independent EXCLUSIVE-OR gates instead of a single complex feedback path. Each EXCLUSIVE-OR gate handles a specific combination of register outputs, allowing the complex polynomial with many terms to be implemented through parallel simpler operations. This segmentation reduces the critical path delay and enables high-speed operation despite using polynomials with 5 or more terms.
Solution Approach 2:
The patent dynamically selects which primitive polynomial to use based on the required error rate and performance requirements. The system can switch between different primitive polynomials (with varying numbers of terms) to optimize the balance between probability distribution characteristic and circuit complexity for different application scenarios.
3Reliability
If the number of feedback paths is increased to improve randomness, then the probability distribution approximates natural noise, but the circuit complexity and manufacturing difficulty increase
Solution Approach 1:
The patent standardizes the design by selecting specific primitive polynomials with predetermined numbers of terms (5 or more) and corresponding structured feedback paths. This parameter standardization allows for optimized manufacturing processes and reduces variability in production, making it easier to manufacture despite the increased number of feedback paths compared to traditional designs.
Data Source
AI summary
An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(α1k), (α2k), (α3k), . . . } falls within a maximum period (2m−1), the group being produced as an element (αk) obtained by raising a root α of a polynomial to a specified power value k (k≧2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (αk) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (αk), the gate supplies the multiplication result as feedback bit data to the respective registers.