M0 Handshake for Dense Library Layout Congestion
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Solution Overview
Problem
The existing semiconductor layouts face challenges in connecting active regions and metal lines to gate lines without violating V0/M0 enclosure rules and maintaining sufficient tip-to-tip distance, particularly in dense library cells, where the introduction of trench silicide and metal 0 layers leads to congestion and manufacturability issues.
Innovation Solution
The solution involves forming M1 metal lines between gate lines and incorporating a double diffusion break at cell boundaries, allowing for a handshake between V0 and M0 segments, which enables connections without conflicts with V0/M0 enclosure rules and maintains the required tip-to-tip distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If M0 is formed wider to satisfy T2T requirements, then manufacturability is improved, but congestion on the M0 level increases
Solution Approach 1:
The patent transitions M0 from a horizontal orientation to a vertical orientation at cell boundaries. This dimensional change allows M0 to satisfy T2T requirements through increased width while simultaneously reducing horizontal congestion on the M0 level by utilizing the vertical space more efficiently.
Solution Approach 2:
The patent applies different M0 configurations in different locations: horizontal M0 segments within cells and vertical M0 segments at cell boundaries. This local differentiation allows each region to optimize for its specific requirements, reducing overall congestion while maintaining manufacturability.
2Reliability
If M0 extends far beyond the edge of V0 to satisfy enclosure rules, then connection reliability is improved, but available space for routing is reduced
Solution Approach 1:
By orienting M0 vertically at cell boundaries rather than horizontally, the patent satisfies V0/M0 enclosure rules in the horizontal direction while freeing up horizontal routing space. The vertical orientation of M0 allows the enclosure requirement to be met without consuming additional horizontal routing resources.
Solution Approach 2:
Instead of extending M0 horizontally to satisfy enclosure rules (which consumes routing space), the patent inverts the approach by extending M0 vertically. This inversion meets the enclosure requirement while preserving horizontal routing space for other connections.
3Device complexity
If traditional dense library layout is used without trench silicide and M0, then layout simplicity is maintained, but pin accessibility and M1 congestion increase
Solution Approach 1:
The patent segments the interconnect function across multiple layers: M0 handles local vertical connections at cell boundaries, while M1 handles horizontal routing. This segmentation improves pin accessibility by providing dedicated vertical access paths without significantly increasing overall layout complexity.
Solution Approach 2:
The patent introduces M0 as an intermediary layer between the substrate and M1. This intermediary provides vertical access to pins and facilitates connections without requiring complex M1 routing, thereby improving pin accessibility while maintaining relative layout simplicity.
Data Source
AI summary
A dense library architecture using an M0 hand-shake and the method of forming the layout are disclosed. Embodiments include forming first and second active areas on a substrate, at the top and bottom of a cell, separated from each other; forming first through third gate lines perpendicular to the active areas, where the first and third gate lines are dummy gates at the cell edges; forming trench silicide segments on each of the active areas, between the first, second, and third gate lines; forming first and second M1 metal lines between the first and second gate lines and the second and third gate lines, respectively; forming a M0 segment between the first and second active regions perpendicular to the M1 metal lines; forming a CB between the M0 segment and the second gate line; and forming a V0 from the first metal line to the M0 segment.