M0 Test Structure for Accurate Contact Impedance Measurement
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Solution Overview
Problem
Conventional testing methods for field-effect transistors and Kelvin field-effect transistors are inefficient as they require formation of higher metallization levels, leading to elevated production costs and delayed detection of failures, as they account for impedance of interconnects in overlying metallization levels.
Innovation Solution
A test structure with a metallization level directly connected to source/drain regions via contacts, allowing for impedance measurement without involving interconnects in overlying metallization levels, thereby minimizing the contribution of these interconnects to impedance determination and enabling earlier detection of failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used with M1 metallization level wiring, then testing can be performed, but production costs are elevated and failure detection is delayed
Solution Approach 1:
The test structure is formed at the M0 metallization level before the M1 metallization level is created. This preliminary action allows testing to occur earlier in the fabrication process, enabling failure detection before additional manufacturing steps are completed, thereby reducing waste and production costs while improving reliability through earlier defect identification
2Measurement precision
If conventional testing with overlying metallization levels is used, then complete interconnect testing is achieved, but impedance measurement accuracy is reduced due to interconnect impedance contributions
Solution Approach 1:
The test structure extracts and isolates the contact impedance measurement from the influence of overlying metallization level interconnects. By positioning the test structure at the M0 level with direct contacts to source/drain regions and using sense connections that bypass M1 interconnects, the measurement system separates the contact impedance being tested from the additional impedance contributions of upper-level interconnect structures, thereby improving measurement precision
3Productivity
If test structures are formed after M1 metallization level, then comprehensive device testing is possible, but testing speed is reduced due to later detection
Solution Approach 1:
The test structure is formed during the M0 metallization level fabrication process as a preliminary action, allowing testing to be performed before M1 metallization level formation. This enables parallel processing where testing can occur earlier in the fabrication sequence, reducing the total fabrication process time and improving productivity by avoiding sequential delays
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach accelerates testing and reduces production costs by allowing earlier identification of failures during the fabrication process, minimizing the impact of interconnect impedance in overlying metallization levels and providing more accurate contact impedance measurements.
Implementation Method 1
One or more contacts are arranged between the metallization level and the device-under-testing. The one or more contacts directly connect the one or more interconnect lines with the one or more source/drain regions.
Implementation Method 2
current is supplied via a pair of connections (i.e., current leads) and a voltage drop occurs allowing the impedance (e.g., resistance) to be measured according to Ohm's law
Data Source
AI summary
Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a test pad, a device-under-testing having one or more source/drain regions, and a metallization level arranged over the device-under-testing. The metallization level includes one or more interconnect lines that are connected with the test pad. One or more contacts, which are arranged between the metallization level and the device-under-testing, directly connect the one or more interconnect lines with the one or more source/drain regions.