MAC Circuit ADC Segmentation for Faster Neural Network Conversion
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Solution Overview
Problem
Current multiply-accumulate (MAC) operations in neural networks are performance-limited due to inefficiencies in converting analog outputs to digital outputs, particularly in determining high and low-order bits, which affects the overall processing speed and accuracy of neural network applications.
Innovation Solution
A MAC computation circuit that includes a bit-cell array generating an analog output, with a first ADC circuit determining the upper part of the digital output by comparing it to coarse ranges and a second ADC circuit determining the lower part by comparing it to fine ranges based on a reference voltage, utilizing a pipeline operation with SAR and flash ADC circuits to enhance precision and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ADC circuit is used to determine both upper and lower parts of digital output, then device complexity is reduced, but measurement precision and conversion efficiency deteriorate
Solution Approach 1:
The patent divides the digital output determination into two separate ADC circuits: a first ADC circuit that determines the upper part (high-order bits) and a second ADC circuit that determines the lower part (low-order bits). This segmentation allows each ADC circuit to be optimized for its specific function, with the first ADC using coarse reference voltages and the second ADC using fine reference voltages, thereby achieving high precision without excessive complexity.
2Productivity
If conventional ADC conversion is used, then device complexity is low, but processing speed and conversion efficiency deteriorate
Solution Approach 1:
The conversion process is segmented into two parallel operations: the first ADC circuit converts the analog output to determine high-order bits while the second ADC circuit simultaneously determines low-order bits using the already-determined high-order bits as reference. This parallel segmentation of the conversion process significantly accelerates the overall conversion speed compared to sequential conventional ADC methods.
3Measurement precision
If high precision conversion is implemented, then measurement precision improves, but conversion time and processing delay increase
Solution Approach 1:
The first ADC circuit performs preliminary conversion to determine the upper part (high-order bits) of the digital output before the second ADC circuit determines the lower part. The result from the first ADC is used as a preliminary reference for the second ADC, enabling the second conversion to be performed faster with reduced uncertainty, thus achieving high precision without proportionally increasing conversion time.
Solution Approach 2:
The conversion process is divided into two time segments: the first ADC circuit operates to determine high-order bits, and the second ADC circuit operates to determine low-order bits using the first ADC's result as a reference. This temporal segmentation allows precision to be achieved in stages rather than requiring all precision operations to complete simultaneously, reducing overall conversion time.
Data Source
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AI summary
A multiply-accumulate (MAC) computation circuit includes: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first analog-to-digital conversion (ADC) circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.