Hardware MAC Address Parser for Wireless Packet Reception
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Solution Overview
Problem
Current wireless communication devices require dual-core processors to manage real-time processing for modem functions and media processing, which is complex, expensive, and power-intensive, while single processors are inadequate due to mutual exclusivity with non-real-time applications.
Innovation Solution
Implementing a single RISC microprocessor with hardware-centric MAC devices and optimized software stack to perform VoIP and VoWLAN functions without a dedicated DSP, using block processing and data locality to minimize data loading and reduce overhead, and employing passive listening for power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual-core processor architecture is used to handle real-time processing for modem functions and media processing, then real-time processing capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the processor into two functional parts: a general-purpose processor for non-real-time applications and a dedicated real-time processor for modem functions and media processing with tight real-time constraints. This segmentation allows each processor to be optimized for its specific function, resolving the contradiction by achieving real-time capability without requiring a complex dual-core architecture.
Solution Approach 2:
The patent introduces a hardware-based MAC device as an intermediary between the real-time processor and the communication medium. This MAC device handles packet address parsing and real-time media access control functions, freeing the real-time processor from routine MAC tasks and allowing it to focus on time-critical signal processing, thereby reducing overall system complexity while maintaining real-time performance.
2Productivity
If a dual-core processor with DSP is used to separate real-time and non-real-time processing, then processing performance is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent employs a general-purpose processor that can be manufactured using standard, cost-effective semiconductor processes rather than requiring expensive DSP-specific fabrication. The real-time processor is designed with simplified architecture that reduces manufacturing complexity while maintaining the necessary processing performance for modem functions and media processing.
3Productivity
If two processors are used to handle real-time and non-real-time functions, then functional performance is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic wake-up mechanisms where the real-time processor enters low-power sleep modes between transmission opportunities and is periodically woken by the general-purpose processor to handle MAC layer packet parsing and address filtering. This periodic action pattern allows the system to maintain functional performance for real-time communication while significantly reducing average power consumption compared to continuously operating dual-processor systems.
Data Source
AI summary
An apparatus comprises a network physical layer and an activity sensor for sensing a packet and activating the network physical layer from shutdown. The network physical layer decodes a PHY header portion and a media access control header portion of a packet header. A MAC has a fixed hardware media access plane implementing IEEE 802.11 series MAC functionality and couples to a microprocessor. A MAC address parser receives the MAC header portion of the packet, for processing the MAC header portion of the packet, and for activating the MAC from a shutdown in response to recognizing a MAC address within the MAC header portion of the packet, such that the MAC is not activated if the MAC parser does not recognize the MAC address, wherein the MAC is operable, after activation, to perform MAC functionality without the microprocessor and to provide data from the packet to the microprocessor.