Multipurpose MAC Array With Independent Operand Routing
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Solution Overview
Problem
Existing digital systems face challenges in efficiently performing multiple types of multiply-accumulate (MAC) operations, such as 3D convolutions, depth-wise convolutions, and matrix multiplications, without requiring burdensome preprocessing of input data.
Innovation Solution
A multipurpose MAC array circuit that allows independent operation of each processing element (PE) to receive operands from configurable memory locations based on operation and data types, eliminating the need for software rearrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed MAC operation architecture is used, then the circuit design is simple, but it cannot handle multiple different types of operations (3D convolutions, depth-wise convolutions, matrix multiplications) without burdensome preprocessing of input data
Solution Approach 1:
The patent implements a universal MAC array architecture where each processing element can perform multiple different MAC operations (3D convolutions, depth-wise convolutions, matrix multiplications, etc.) by selectively coupling to different memory locations. The same physical circuit hardware is configured through different operand selection to execute various operation types, eliminating the need for separate dedicated circuits for each operation type.
Solution Approach 2:
The patent introduces dynamic configurability through selective coupling mechanisms that allow processing elements to adaptively connect to different memory locations based on the operation type being executed. This dynamic reconfiguration enables the same hardware to serve multiple functions without requiring physical reconfiguration or complex preprocessing of input data.
2Productivity
If software preprocessing and manipulation of input data is required for different MAC operations, then a fixed MAC architecture can be used, but processing time and computational efficiency are reduced
Solution Approach 1:
The patent performs preliminary organization of data in memory structures that are optimized for different operation types. By pre-arranging data in memory with appropriate addressing schemes, the system eliminates the need for runtime data manipulation and preprocessing, allowing processing elements to directly access required operands without software intervention.
Solution Approach 2:
The patent introduces memory structures with selective coupling capabilities as an intermediary between data storage and processing elements. This intermediary layer handles the complexity of data reorganization and operand selection, allowing processing elements to receive properly configured operands without requiring complex preprocessing operations.
3Ease of operation
If each processing element receives operands from the same memory locations, then memory access is simplified, but the ability to perform different operation types independently is limited
Solution Approach 1:
The patent segments the memory access paths for each processing element, allowing independent selective coupling to different memory locations. Each processing element has its own configurable memory interface that can be independently directed to appropriate data sources based on the operation type, enabling both simple memory access and high operational versatility.
Data Source
AI summary
Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled to the one or more input memories to receive at least a pair of operands and generate a result. Each of the plurality of multiply-accumulator circuits receives operands from the one or more input memories independently. Additionally, selection of operands from the one or more input memories is controlled based on at least an operation and/or data types, where different operation and/or data types configure the plurality of multiply-accumulator circuits to receive different pairs of operands from the one or more input memories to execute particular operation types.