MAC Array Segmentation for Matrix Multiplication
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Solution Overview
Problem
Current microprocessor architectures face limitations in efficiently performing matrix multiplication due to constraints on data movement between arithmetic logical units, register files, and memory, which restrict the number of arithmetic operations that can be executed in a single instruction, and increasing vector length requires substantial additional cost and power consumption.
Innovation Solution
A Multiply Accumulator (MAC) array comprising M × N MAC units arranged in M rows and N columns, each with a multiply unit, an accumulator unit, and multiple register units, allowing flexible data distribution and execution of matrix multiplication operations, thereby increasing arithmetic operations per processor cycle and reducing memory bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector length is increased to execute more arithmetic operations per instruction, then arithmetic operation performance is improved, but processor cost and power consumption increase substantially
Solution Approach 1:
The processor divides the arithmetic execution engine into multiple independent MAC units arranged in an array, where each MAC unit can independently execute multiply-accumulate operations. This segmentation allows parallel execution of multiple operations without requiring a single oversized vector unit, thus improving arithmetic performance while keeping individual unit complexity and power consumption manageable.
Solution Approach 2:
The invention transitions from a single-dimensional vector processing approach to a two-dimensional MAC unit array architecture (M rows × N columns). This dimensional change enables parallel execution across multiple MAC units simultaneously, achieving higher arithmetic operation throughput without proportionally increasing the complexity of each individual processing element.
2Productivity
If the number of execution units is increased to improve matrix multiplication efficiency, then productivity is improved, but data movement constraints between arithmetic logical units, register files, and memory become more severe
Solution Approach 1:
The MAC unit combines the multiplier and accumulator functions into a single integrated hardware component, reducing the need for separate functional blocks and their associated data movement interfaces. This merging minimizes data movement constraints while maintaining high execution unit density for improved matrix multiplication efficiency.
Solution Approach 2:
Each MAC unit in the array is designed as a universal processing element that can handle multiple operations (multiplication, accumulation, and register operations) within a single integrated structure. This multi-functionality reduces the overall system complexity by eliminating the need for specialized functional blocks for each operation type.
3Adaptability or versatility
If MAC units are implemented as hardware components with multiple register units, then flexibility and out-of-order execution capability are improved, but device complexity increases
Solution Approach 1:
The MAC unit includes multiple register units that can pre-load and hold input data before it is needed for computation. This preliminary action enables out-of-order execution by allowing the control logic to fetch and prepare data in advance, improving execution flexibility without significantly increasing the core computational complexity.
Data Source
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AI summary
The present invention presents a Multiply Accumulator, MAC, Array, comprising M x N MAC units 10 arranged in M rows and N columns, each of the M rows of MAC units 10 being connected to one of M data inputs and each of the N columns of MAC unit 10 being connected to one of N data inputs, M and N being natural numbers, wherein each MAC unit 10 comprises a multiply unit 13 having two inputs and one output, an accumulator unit 14 having a first and a second accumulator input and one accumulator output, and a plurality of register units 15 having one input and one output, wherein, in each MAC unit 10, a first data input from the M data inputs and a second data input from the N data inputs form the two inputs of the multiply unit 13, the output of the multiply unit 13 forms the first accumulator input and the output of the plurality of register units 15 forms the second accumulator input, and the accumulator output forms the input of the plurality of register unit 15, wherein the MAC units 10 are implemented as hardware components. The invention is further directed to a processor device comprising such a MAC array and an instruction decoder.