MAC Assist Memory Unit for CNN In-Memory Computing
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Solution Overview
Problem
State-of-the-art non-volatile memory (NVM) for Computation-in-Memory (CIM) applications faces challenges such as process variation in NVM cells, high leakage current in high resistance state (HRS) cells, and large DC current, which affect the energy efficiency and accuracy of multiply-accumulate (MAC) operations for multi-bit convolutional neural networks (CNNs).
Innovation Solution
A memory unit with a multiply-accumulate (MAC) assist scheme that includes a non-volatile memory cell, a voltage divider, and a voltage keeper, controlled by a reference voltage and multi-bit input voltage, which generates a charge current and output current to calibrate cell variations and eliminate leakage currents, thereby improving energy efficiency and inference accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If non-volatile memory (NVM) is used for computing-in-memory applications, then energy efficiency is improved, but process variation in NVM cells degrades the accuracy of multiply-accumulate operations
Solution Approach 1:
The patent applies preliminary calibration actions before actual MAC operations. The calibration process pre-characterizes NVM cells and stores correction data, which is then used to compensate for process variations during inference. This preliminary characterization eliminates the need for complex real-time calibration circuits while maintaining high accuracy.
Solution Approach 2:
The patent introduces intermediary calibration data and correction mechanisms that mediate between the physical NVM cell variations and the computational requirements. The calibration information acts as an intermediary layer that translates physical variations into corrected computational values, enabling accurate MAC operations despite cell variations.
2Quantity of substance
If high resistance state (HRS) cells are used in NVM, then storage capacity is improved, but leakage current increases and degrades energy efficiency
Solution Approach 1:
The patent extracts and eliminates the harmful leakage current from HRS cells through calibration-based compensation. By measuring and characterizing the leakage characteristics during calibration, the system can subtract or compensate for these leakage effects during actual computation, allowing HRS cells to be used for increased storage capacity without suffering from their inherent leakage problems.
3Speed
If conventional NVM MAC operations are performed, then computing speed is improved, but large DC current increases power consumption
Solution Approach 1:
The patent implements periodic calibration actions rather than continuous calibration during all operations. The calibration is performed periodically or upfront, and the corrected parameters are then used for multiple subsequent MAC operations. This periodic approach maintains high computing speed while reducing overall power consumption compared to continuous calibration schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively calibrates NVM cell variations and reduces large DC currents, enhancing energy efficiency and linearity in MAC operations for multi-bit CNN applications, leading to improved performance and reduced power consumption.
Implementation Method 1
The voltage divider is connected to the non-volatile memory cell and controlled by the reference voltage. The voltage divider includes a data line and generates a charge current on the data line according to the reference voltage
Implementation Method 2
The non-volatile memory cell is controlled by the word line and stores a weight
Data Source
AI summary
A memory unit with a multiply-accumulate assist scheme for a plurality of multi-bit convolutional neural network based computing-in-memory applications is controlled by a reference voltage, a word line and a multi-bit input voltage. The memory unit includes a non-volatile memory cell, a voltage divider and a voltage keeper. The non-volatile memory cell is controlled by the word line and stores a weight. The voltage divider includes a data line and generates a charge current on the data line according to the reference voltage, and a voltage level of the data line is generated by the non-volatile memory cell and the charge current. The voltage keeper generates an output current on an output node according to the multi-bit input voltage and the voltage level of the data line, and the output current is corresponding to the multi-bit input voltage multiplied by the weight.