Resistor-Capacitor MAC Circuit Timing for Parasitic Capacitance Compensation
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Solution Overview
Problem
Parasitic capacitance in circuits performing MAC operations leads to erroneous results, affecting the performance and efficiency of applications such as machine learning, where a large number of MAC operations are required.
Innovation Solution
A method and apparatus utilizing a resistor group with parasitic capacitance, where the sampling capacitor voltage and power supply unit voltage are controlled through specific reference voltages and time points to perform MAC operations accurately, minimizing the impact of parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parasitic capacitance is present in the circuit performing MAC operations, then the circuit can be implemented with standard components, but erroneous operation results occur
Solution Approach 1:
The patent measures the parasitic capacitance effect through timing measurements and uses this information to correct the MAC operation results. The harmful parasitic capacitance is converted into a measurable parameter that can be compensated for, transforming the problem into a solution.
Solution Approach 2:
The patent implements a feedback mechanism where the timing information from the sampling capacitor voltage reaching reference voltages is used to correct the MAC operation results. This feedback loop allows the system to compensate for parasitic capacitance effects dynamically.
2Measurement precision
If the sampling capacitor voltage is monitored continuously to determine switching time, then accurate timing control is achieved, but power consumption increases
Solution Approach 1:
The patent uses periodic threshold comparisons instead of continuous monitoring. The sampling capacitor voltage is compared against reference voltages at specific intervals to determine when switching should occur, reducing power consumption while maintaining timing accuracy.
Solution Approach 2:
The patent introduces reference voltages as intermediaries to facilitate the timing measurement. By comparing the sampling capacitor voltage against these reference levels, the system can determine switching times accurately without requiring complex continuous monitoring circuitry.
3Reliability
If the power supply unit is floated at switching time, then parasitic capacitance impact is reduced, but circuit control complexity increases
Solution Approach 1:
The patent performs preliminary timing measurements and determines switching times before executing the MAC operations. This preliminary action allows the system to prepare the power supply unit in advance, reducing parasitic capacitance impact without adding complex real-time control mechanisms.
Solution Approach 2:
The patent dynamically adjusts the power supply unit state based on the measured timing information. The power supply is floated at specific moments determined by when the sampling capacitor voltage reaches reference levels, creating a dynamic control scheme that adapts to the actual circuit behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures accurate and efficient MAC operations by compensating for parasitic capacitance, thereby improving the reliability and speed of applications like machine learning.
Implementation Method 1
a sampling capacitor. A parasitic capacitance exists at each node between the plurality of resistors
Implementation Method 2
A parasitic capacitance exists in a circuit that performs a MAC operation, which may result in an erroneous MAC operation result
Implementation Method 3
determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time
Data Source
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AI summary
A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.