MAC Interpacket Gap Control for Network Clock Rate Mismatch

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Solution Overview

Problem

Network interfaces experience inefficiencies due to clock rate mismatches, leading to data loss when transmitting data between devices with varying clock rates, which can result in dropped data units.

Innovation Solution

Implementing idle insertion and reduction logic in the MAC layer of network interfaces to adjust the number of idle bytes between data units, compensating for clock rate variances and increasing transmission bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transmitted between network devices with different clock rates, then data transmission occurs, but clock rate mismatches cause data loss and dropped data units

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by inserting idle bytes into data units before transmission to proactively compensate for clock rate mismatches. The network device calculates the clock rate difference and pre-inserts the required number of idle bytes into each data unit, ensuring that the transmitted data stream aligns with the receiving device's clock rate, thereby preventing data loss due to timing mismatches

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the number of idle bytes inserted into data units based on the calculated clock rate difference. The system modifies the structure of data units by varying the idle byte count according to the formula: idle bytes = ceiling((transmit clock rate - receive clock rate) / receive clock rate * data unit size), thereby adapting the transmission parameters to match the receiving device's clock characteristics

Inventive Principle:
Principle #35Parameter changes

2Reliability

If idle bytes are inserted to compensate for clock rate variance, then data loss is reduced, but transmission bandwidth is decreased

Engineering Contradiction:
Improvedata integrityVSAvoidtransmission bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by inserting only the minimum necessary number of idle bytes to compensate for clock rate mismatches. Rather than inserting excessive idle bytes, the system calculates the precise number needed based on the clock rate difference and inserts only that amount, thereby maintaining data integrity while minimizing the impact on transmission bandwidth

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the idle byte insertion based on the actual clock rate difference. The system modifies the idle byte parameter according to the receiving device's clock characteristics, ensuring that only the necessary compensation is applied, thereby optimizing the balance between data integrity and transmission efficiency

Inventive Principle:
Principle #35Parameter changes

3Productivity

If clock rate variance is compensated by adjusting idle bytes, then data units are transmitted successfully, but complex calculations and determinations are required

Engineering Contradiction:
Improvedata transmission success rateVSAvoidcalculation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the transmitting network device to automatically determine its own clock rate and the receiving device's clock rate, then autonomously calculate the difference and insert the appropriate number of idle bytes without external intervention. The device serves itself by monitoring its own performance and making real-time adjustments to compensate for clock rate mismatches

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent applies feedback by using the received clock rate information from the receiving device to adjust the idle byte insertion. The transmitting device receives clock rate feedback, calculates the difference, and uses this information to dynamically adjust the number of idle bytes inserted into subsequent data units, creating a closed-loop system that continuously optimizes transmission

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12494943B1Handling interface clock rate mismatches between network devices
Publication Date: 2025.12.09 INNOVIUM INC
  • US12494943B1 patent drawing
  • US12494943B1 patent drawing
  • US12494943B1 patent drawing

AI summary

The performance of a switch or other network device is improved by adjusting the number of idle bytes transmitted between data units—that is, the size of the interpacket gap—to increase the bandwidth of a network interface. In some embodiments, the adjustments may be made in a manner designed to compensate for potential mismatches between the clock rate of the network interface and clock rates of interfaces of other network devices when retransmitting data received from those other network devices. In yet other embodiments, the adjustments may be designed to increase available bandwidth for other purposes. In an embodiment, the idle reduction logic is in a Media Access Control (“MAC”) layer of a network interface. The idle reduction logic may be enabled or disabled based on user preference, or programmatically based on factors such as a transmission utilization level for the MAC layer, buffer fill level, and so forth.