MAC-hs PDU Disassembly in HSDPA Receiver

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Solution Overview

Problem

In third-generation (3G) wireless communication systems, the high data transfer rates and broadband capabilities, especially in HSDPA mode, create processing bottlenecks due to bit-shifting operations required for disassembly and decryption, which are inefficiently handled by Protocol Stack (PS) processors, leading to potential delays in data processing and transmission.

Innovation Solution

Reassigning disassembly and decryption functions from PS processors to baseband processors, which are better suited for bit-manipulating operations, and restructuring the MAC-hs entity to perform reordering in the PS processor, reducing the need for bit-shifting in the UE's MAC-d entity and RLC layer, thus optimizing processor utilization and meeting the stringent Transmission Time Interval (TTI) requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If disassembly and decryption functions are handled by Protocol Stack (PS) processors, then the system can process data packets, but processing efficiency deteriorates due to bit-shifting operation bottlenecks

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidprocessing delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the data processing functions by separating disassembly and decryption operations from the PS processor and assigning them to baseband processors. This segmentation allows bit-intensive operations to be handled by specialized hardware while the PS processor focuses on higher-level protocol processing, thereby improving overall processing efficiency and reducing delays in HSDPA data packet handling.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a reordering entity as an intermediary component that receives data packets from the baseband processor, performs reordering based on transmission sequence numbers, and then forwards packets to the MAC-d entity. This intermediary structure optimizes the data flow between layers, reducing processing bottlenecks and improving throughput by enabling parallel processing of reordering operations independent of bit-shifting operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If MAC-hs entity performs reordering operations, then data packet ordering is improved, but processing complexity increases in the PS processor

Engineering Contradiction:
Improvedata packet ordering accuracyVSAvoidprocessor operational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the reordering function from the MAC-hs entity in the PS processor and implements it as a separate reordering entity that operates independently. This extracted reordering entity receives packets with transmission sequence numbers from the baseband processor and performs reordering based on these numbers, thereby maintaining reliable data packet ordering while reducing the operational complexity and processing burden on the PS processor.

Inventive Principle:
Principle #2Taking out (Extraction)

3Speed

If baseband processors handle bit-manipulating operations, then processing speed improves, but the need for coordination with PS processors increases

Engineering Contradiction:
Improvebit-processing speedVSAvoidinter-processor coordination complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges the disassembly and decryption functions with the baseband processor, combining bit-manipulating operations in a single processing unit. This merging eliminates the need for frequent coordination and data transfer between baseband and PS processors for these specific operations, thereby achieving high-speed bit processing while actually reducing inter-processor coordination complexity through functional integration.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8660145B2MAC-HS processing in an HSDPA-compatible receiver in a 3G wireless network
Publication Date: 2014.02.25 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8660145B2 patent drawing
  • US8660145B2 patent drawing
  • US8660145B2 patent drawing

AI summary

In one embodiment, a method for processing a series of MAC-hs protocol data units (PDUs) in an HSDPA-compatible (high-speed downlink packet access) receiver in a 3G wireless communication network, the method including: (a) receiving a MAC-hs PDU having: (i) a queue identification (QID), (ii) a transmission sequence number (TSN), and (iii) one or more MAC-d PDUs, (b) then disassembling the MAC-hs PDU (c) then distributing the one or more MAC-d PDU to a reordering queue indicated by the QID, and (d) then performing reordering processing for the corresponding reordering queue based on the TSN. Steps (a) and (b) are performed in a physical layer of the receiver. Steps (c) and (d) are performed in a data-link layer of the receiver.