Integrating MAC and PCS Modules to Eliminate Rate Adapting FIFO
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Solution Overview
Problem
Existing high-speed Ethernet interface circuits face challenges in maintaining the minimum required Inter Packet Gap (IPG) during frame construction, leading to inefficiencies and increased circuitry due to the need for rate adapting FIFOs and complex intermediate interfaces.
Innovation Solution
A packet network interface apparatus with a MAC module, a PCS module, and an inter packet gap module that operates within a single clock domain, eliminating the need for a rate adapting FIFO and integrating MAC and PCS functions, allowing direct data transfer while maintaining the IPG by deleting or inserting idle characters, and using gapping logic to ensure the IPG meets the IEEE 802.3 specification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rate adapting FIFO and complex intermediate interfaces are used to maintain IPG, then IPG compliance is achieved, but circuit complexity and size increase
Solution Approach 1:
The patent combines the MAC and PCS modules into a single integrated interface apparatus, eliminating the need for separate rate adapting FIFOs and complex intermediate interfaces. The MAC module directly interfaces with the PCS module through a simplified internal connection, merging functions that were previously separated into distinct components with intermediate buffering.
Solution Approach 2:
The patent extracts and eliminates the rate adapting FIFO from the system by implementing a single clock domain architecture. The IPG maintenance function is achieved directly through the integrated MAC-PCS interface without requiring separate buffering components, removing unnecessary complexity while maintaining compliance.
2Adaptability or versatility
If rate adapting FIFO is used for data buffering, then data rate adaptation is achieved, but circuit size increases
Solution Approach 1:
The patent merges the clock domains of MAC and PCS into a single unified clock domain, eliminating the need for rate adapting FIFOs. Data buffering is achieved through the inherent timing synchronization of the integrated architecture rather than separate buffering components, reducing circuit size while maintaining adaptability.
3Productivity
If physical xMII interface is implemented, then data transfer capability is achieved, but circuit complexity increases
Solution Approach 1:
The patent extracts and eliminates the physical xMII interface by implementing direct internal interfacing between MAC and PCS modules. Data transfer is maintained through this simplified internal connection, removing the complexity of physical intermediate interfaces while preserving full data transfer capability.
Solution Approach 2:
The patent merges the MAC and PCS modules into a single integrated unit with direct internal communication paths. This integration eliminates the need for separate physical interfaces like xMII, reducing interface complexity while maintaining productive data transfer between layers.
Data Source
AI summary
A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.