MAC-PHY One-Step Timestamping for Lower-Complexity Timing Packets
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Solution Overview
Problem
Two-step timestamping in network devices increases overhead and implementation complexity, while one-step timestamping enhances hardware requirements and power consumption.
Innovation Solution
A network device processes timing packets by generating initial timing information at a MAC or host processor and providing indicators to a PHY device for efficient on-the-fly embedding, reducing hardware and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate timestamping procedures are used, then security and integrity of data packets are ensured, but processing time increases and system complexity increases
Solution Approach 1:
The patent combines the timestamping operation with the existing packet processing operation into a single integrated step. The timestamp is generated and inserted into the packet header during the same processing cycle that handles packet routing and forwarding, eliminating the need for separate timestamping procedures and reducing total processing time while maintaining security and integrity through cryptographic signing.
Solution Approach 2:
The patent performs timestamping as a preliminary action within the existing packet processing pipeline rather than as a subsequent separate step. By integrating the timestamp generation and insertion into the initial packet handling phase, the system ensures that time-stamped packets are ready for immediate forwarding without requiring additional processing cycles, thus reducing overall processing time while maintaining reliability.
2Reliability
If traditional separate timestamping procedures are used, then security and integrity of data packets are ensured, but device complexity increases
Solution Approach 1:
The patent merges the timestamping function with existing packet processing components into a single integrated operation. By combining these functions, the patent eliminates the need for separate timestamping hardware or software modules, reducing system complexity while maintaining security and integrity through the unified processing approach that leverages existing cryptographic capabilities.
Solution Approach 2:
The patent makes the packet processing system multi-functional by enabling it to perform both packet routing/forwarding and timestamping operations within the same processing pipeline. This universal approach allows a single system component to handle multiple functions that were previously requiring separate dedicated modules, thereby reducing overall system complexity while maintaining the security and integrity requirements.
3Productivity
If timestamping is integrated into packet processing, then processing time decreases, but ensuring security and integrity becomes more challenging
Solution Approach 1:
The patent combines timestamping with packet processing in a way that maintains security and integrity by performing cryptographic signing operations as part of the integrated process. The merging is designed so that the timestamp is cryptographically bound to the packet contents during the same processing cycle, ensuring that the integrated approach does not compromise security while achieving faster processing.
Solution Approach 2:
The patent uses cryptographic signatures as an intermediary mechanism that bridges the integrated packet processing and timestamping operations. This intermediary ensures that even though the operations are merged into a single step, the security and integrity are maintained through cryptographic verification that the timestamp has not been tampered with and is authentically bound to the packet contents.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.