Mac Processing Pipeline With Conversion Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multiplier-accumulator circuits face inefficiencies in data throughput and processing speed, particularly when handling floating-point data formats, as they often require conversion between formats to facilitate Winograd processes, which can complicate data processing and reduce performance.
Innovation Solution
The integration of conversion circuitry within the multiplier-accumulator pipelines to convert data between floating-point and fixed-point formats, specifically using block-scaled fraction formats, allows for efficient implementation of Winograd processes, enhancing data throughput by enabling seamless processing in both formats within the pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is converted between floating-point and fixed-point formats to facilitate Winograd processes, then processing compatibility is improved, but device complexity increases
Solution Approach 1:
The patent combines the floating-point to fixed-point conversion circuitry and fixed-point to floating-point conversion circuitry directly within the MAC pipeline structure. This integration allows the pipeline to handle both data formats seamlessly, improving processing compatibility while avoiding the need for separate external conversion units that would increase device complexity.
Solution Approach 2:
The MAC pipeline is designed with multi-functional conversion circuitry that can operate in multiple modes: processing floating-point data directly, converting floating-point to fixed-point for Winograd processes, and converting fixed-point back to floating-point. This universal design allows a single pipeline to handle various data processing scenarios without requiring separate specialized circuits.
2Productivity
If conversion circuitry is integrated within the MAC pipeline, then data throughput is improved, but device complexity increases
Solution Approach 1:
The conversion circuitry is merged with the MAC pipeline stages, allowing data to flow continuously through conversion and processing operations without external intervention. This integration eliminates data transfer bottlenecks between separate conversion units and processing units, thereby improving data throughput while keeping the overall device structure unified.
Solution Approach 2:
The floating-point to fixed-point conversion is performed preliminarily within the pipeline before the main Winograd processing operations. This preliminary conversion prepares the data in the appropriate format for subsequent high-speed fixed-point arithmetic operations, enabling the pipeline to maintain high throughput by avoiding format conversion bottlenecks during critical processing stages.
3Speed
If continuous floating-point processing is enabled, then processing speed is improved, but compatibility with Winograd processes deteriorates
Solution Approach 1:
The MAC pipeline incorporates dynamic format switching capability, allowing it to adapt its operational mode based on the processing requirements. When Winograd processes are needed, the pipeline dynamically switches to fixed-point mode through the integrated conversion circuitry. When continuous floating-point processing is beneficial, it operates in floating-point mode, thereby achieving both high processing speed and Winograd process compatibility.
Solution Approach 2:
The integrated conversion circuitry acts as an intermediary between floating-point input data and the fixed-point Winograd processing stages. This intermediary component enables seamless transition between data formats, allowing the pipeline to accept floating-point data, convert it to fixed-point for Winograd operations, and then convert results back to floating-point, thereby maintaining both processing speed and Winograd compatibility.
Data Source
AI summary
An integrated circuit including a multiplier-accumulator execution pipeline including a plurality of multiplier-accumulator circuits to process the data, using filter weights, via a plurality of multiply and accumulate operations. The integrated circuit includes first conversion circuitry, coupled the pipeline, having inputs to receive a plurality of sets of data, wherein each set of data includes a plurality of data, Winograd conversion circuitry to convert each set of data to a corresponding Winograd set of data, floating point format conversion circuitry, coupled to the Winograd conversion circuitry, to convert the data of each Winograd set of data to a floating point data format. In operation, the multiplier-accumulator circuits are configured to perform the plurality of multiply and accumulate operations using the data of the plurality of Winograd sets of data from the first conversion circuitry and the filter weights, and generate output data based on the multiply and accumulate operations.