MAC Processor Architecture with Tightly Coupled Memory
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Solution Overview
Problem
Media access control (MAC) systems in WiMAX communication systems, such as those conforming to the IEEE 802.16e Standard, are complex and expensive due to the orthogonal frequency division multiple access (OFDMA) multiplexing scheme, which requires efficient processing of data across multiple bursts and subcarriers within communication frames.
Innovation Solution
A MAC processor comprising a programmable controller and a hardware processor, tightly coupled with memory, to process and store data indicating the structure of downlink data within communication frames, allowing for efficient implementation of MAC functions by directly storing critical information in tightly coupled memory and system memory via a system bus, facilitating context switching and error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If OFDMA multiplexing is used to handle multiple bursts and subcarriers, then communication capacity and resource utilization are improved, but MAC system complexity and implementation cost increase
Solution Approach 1:
The MAC processor is segmented into distinct functional units: a programmable controller for MAC function execution, a hardware processor for frame processing, tightly coupled memory for critical data, and system memory for general data. This segmentation allows each component to specialize in specific tasks, managing the complexity of OFDMA multiplexing through modular architecture while maintaining high communication capacity.
2Ease of operation
If all data in communication frames is stored in system memory, then memory management is simplified, but processing speed and latency increase due to bus access overhead
Solution Approach 1:
Critical data indicating the structure of downlink data is extracted from the general data stream and stored separately in tightly coupled memory associated with the programmable controller. This extraction eliminates the need for frequent system bus accesses during MAC processing, significantly improving processing speed and reducing latency while maintaining simplified memory management through clear data classification.
3Loss of time
If critical downlink structure data is stored in tightly coupled memory, then processing latency is reduced, but hardware complexity increases due to additional memory components
Solution Approach 1:
The tightly coupled memory is merged with the programmable controller as an integrated component, with the memory directly associated with and accessible by the controller without requiring external bus interfaces. This merging reduces processing latency for critical downlink structure data while minimizing hardware complexity by eliminating separate memory controllers and external connection interfaces.
Data Source
AI summary
In a media access control (MAC) processor, a programmable controller is configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A tightly coupled memory is associated with the programmable controller. A system memory is coupled to the programmable controller via a system bus, and a hardware processor is coupled to the system bus and the tightly coupled memory. The hardware processor is configured to implement MAC functions on data received in a communication frame, store, in the tightly coupled memory, processed data corresponding to data in the communication frame that indicates a structure of downlink data in the communication frame, and store, in the system memory, processed data corresponding to other data in the communication frame.