Hardware Sort Coprocessor for MAC Scheduler Packet Prioritization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing mobile wireless communication systems face challenges in effectively prioritizing packet transfers to meet specified quality of service parameters such as bit error rate, packet latency, and signal-to-noise ratio, which complicates traffic management.
Innovation Solution
A hardware-based sort coprocessor is integrated with a Media Access Control (MAC) scheduler to generate a sorted array of packets based on specified priority parameters, improving packet processing efficiency by utilizing shared memory and processing requests to allocate radio resources effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based sorting is used in MAC scheduler, then implementation flexibility is maintained, but processing speed and response time deteriorate
Solution Approach 1:
A hardware-based sort coprocessor is introduced as an intermediary component between the MAC scheduler and the main processor. The coprocessor handles sorting operations in hardware, significantly improving packet processing speed while reducing the computational burden on the main processor. The coprocessor communicates with the MAC scheduler through shared memory, enabling efficient data exchange without bottlenecking the main processing path.
2Reliability
If more processor resources are allocated for packet prioritization, then quality of service parameter compliance improves, but device complexity and cost increase
Solution Approach 1:
The packet processing function is segmented into distinct components: the MAC scheduler handles high-level scheduling decisions, while the hardware sort coprocessor handles the computationally intensive sorting and prioritization tasks. This segmentation allows each component to be optimized for its specific function, ensuring quality of service compliance without requiring the main processor to handle all processing tasks alone.
3Productivity
If hardware-based sort coprocessor is added, then packet processing efficiency improves, but device complexity increases
Solution Approach 1:
The hardware sort coprocessor is designed as a universal sorting engine that can handle various sorting algorithms and priority schemes through configurable parameters. The coprocessor interface and shared memory structure are designed to be generic, allowing the same hardware component to serve different MAC scheduler requirements without requiring custom hardware design for each scenario.
Data Source
AI summary
An apparatus includes a Media Access Control (MAC) scheduler to generate a sort request. A hardware based sort coprocessor services the sort request in accordance with specified packet processing priority parameters to generate a sorted array.