MAC Streaming Path Using On-Chip Memory for Low-Latency TSN
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Solution Overview
Problem
Existing Ethernet TSN controllers face latency issues in transporting data within a system-on-a-chip (SOC) or host device, particularly in applications requiring precise scheduling like collision avoidance warnings, due to the lack of industry standards addressing latencies in data transportation between services and service devices.
Innovation Solution
Implementing a modified Direct Memory Access (DMA) streaming technique that bypasses off-chip memory access by using a single descriptor and on-circuit memory, reducing software intervention and establishing a hardware path between network and device control circuitry to manage data flow directly to/from on-board memory, thereby minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional DMA streaming is used with off-chip memory access, then data transfer capability is maintained, but latency increases to 35 ms
Solution Approach 1:
The patent extracts the memory access path from off-chip memory to on-circuit memory, separating the data transfer path from the traditional DMA path. This extraction eliminates the latency-prone off-chip memory access while maintaining data transfer capability, reducing latency from 35 ms to under 1 ms.
Solution Approach 2:
The patent introduces an intermediary hardware path between the network controller and on-circuit memory, bypassing the traditional software-mediated DMA path. This intermediary path enables direct hardware-based data transfer, eliminating software intervention and reducing latency.
2Productivity
If software intervention is used for DMA management, then control flexibility is maintained, but computational burden increases
Solution Approach 1:
The patent implements self-service by enabling the hardware to manage its own data transfer operations independently of software intervention. The on-circuit memory and hardware path automatically handle data transfer, freeing the CPU from computational burdens while maintaining operational flexibility through hardware-based control.
Solution Approach 2:
The patent substitutes the software-based mechanical control system with a hardware-based automatic control system. This replacement eliminates software computational burdens while maintaining control flexibility through hardware registers and control logic, improving productivity.
3Loss of time
If on-circuit memory is used with single descriptor, then latency is reduced to under 1 ms, but memory access pattern becomes more constrained
Solution Approach 1:
The patent implements dynamics by enabling flexible memory access patterns through hardware-based control mechanisms. The system can dynamically adjust access patterns based on data requirements while maintaining low latency through the optimized on-circuit memory path, resolving the contradiction between speed and flexibility.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed to manage streaming. An example system includes interface circuitry and media access control (MAC) circuitry to route data from a network to a single address of a memory based on a memory address pointer at a scheduled rate.