Floating-Point to Fixed-Point MACC Mapping for Strided Convolutions
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Solution Overview
Problem
Existing convolution techniques in deep learning are limited by the inability to perform parallel generalized convolutions due to conflicts between shift registers and stride or dilation in convolution operations, which restrict the use of striding or dilated convolutions.
Innovation Solution
The implementation of a software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators, including a multiply-accumulate circuit with a scaler and control circuit that provides control data for bit index selection and right shifts, enabling efficient bit selection and processing in convolutional neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If shift registers are used to cycle through samples in sequence, then the convolution operation can be performed with simple sequential processing, but striding or dilated convolutions cannot be implemented
Solution Approach 1:
The patent segments the convolution computation into multiple parallel processing paths within the DSP array, allowing different regions to handle different spatial positions simultaneously. This segmentation enables striding and dilated convolutions by assigning specific spatial patterns to different processing elements, resolving the conflict between sequential simplicity and operational versatility.
Solution Approach 2:
The patent introduces a spatial dimension parallelism by organizing DSPs in a two-dimensional array where both horizontal and vertical dimensions can process different spatial locations simultaneously. This dimensional transformation allows the system to perform striding and dilated convolutions by leveraging the spatial arrangement of processing elements rather than sequential time-based processing.
2Measurement precision
If floating-point multiply-accumulate units are used, then high precision computation is achieved, but hardware resource consumption and complexity increase
Solution Approach 1:
The patent dynamically changes the precision parameters of the multiply-accumulate units based on the specific convolution layer and data characteristics. Different layers can use different precision levels (e.g., 16-bit, 32-bit, or custom precision), allowing the system to achieve high precision where needed while reducing hardware complexity in other regions, thus resolving the trade-off between precision and resource consumption.
Solution Approach 2:
The patent implements dynamic precision adjustment where the precision of floating-point operations can be changed at runtime based on the computational requirements of different layers. This dynamic adaptation allows the system to use higher precision for critical layers requiring accuracy while using lower precision for layers where approximate results suffice, optimizing the balance between computation precision and hardware complexity.
Data Source
AI summary
An example multiply accumulate (MACC) circuit includes a multiply-accumulator having an accumulator output register, a scaler, coupled to the multiply accumulator, and a control circuit coupled to the multiply-accumulator and the scaler. The control circuit is configured to provide control data to the scaler, the control data indicative of: a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register for implementing a first right shift; a multiplier; and a second right shift.