Machine Learning HTF DRC Prediction for Circuit Layout ECO Fixes
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Solution Overview
Problem
Existing IC design processes face challenges in identifying and efficiently addressing hard-to-fix (HTF) design rule check (DRC) violations, leading to excessive manual effort and inefficiencies in chip design and manufacturing.
Innovation Solution
A machine learning-based system is employed to predict HTF DRC violations by training a model on past data, utilizing features like metal layer densities and cell densities to classify DRC violations, thereby minimizing redundant fix iterations and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional manual methods are used to identify and fix DRC violations, then design accuracy can be maintained through human expertise, but productivity is significantly reduced due to excessive manual effort and redundant fix iterations
Solution Approach 1:
A machine learning model is introduced as an intermediary between the DRC violation detection system and the fix iteration process. The model predicts whether a DRC violation is hard-to-fix based on extracted features, enabling automated prioritization and reducing manual intervention time while maintaining accuracy through learned patterns from training data
Solution Approach 2:
The system performs preliminary classification of DRC violations as hard-to-fix or easy-to-fix before the actual fix process begins. By predicting fix difficulty in advance using trained models and extracted features, the system prepares prioritized action plans that reduce redundant iterations and focus manual effort on truly difficult cases
2Measurement precision
If comprehensive feature analysis is performed to improve prediction accuracy, then measurement precision of HTF DRC violations increases, but device complexity of the prediction system increases
Solution Approach 1:
The prediction system is segmented into distinct functional modules: a feature extraction module that identifies relevant characteristics from circuit layouts, a model training module that learns from labeled data, and a prediction module that classifies new violations. This modular architecture manages complexity while enabling comprehensive feature analysis through specialized components
Solution Approach 2:
The system transforms complex layout data into standardized numerical features that capture essential characteristics. By changing the parameter representation from raw geometric data to extracted features (such as spatial relationships, pattern types, and contextual attributes), the system achieves high prediction accuracy while managing computational complexity through dimensionality reduction
Data Source
AI summary
A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.


