Macro-Aware Power Planning for SoC Voltage Drop
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Solution Overview
Problem
The increasing complexity of power planning in modern system-on-a-chip (SoC) designs due to shrinking feature sizes and higher dynamic power consumption, coupled with the need for efficient power delivery and reduced voltage drop, poses challenges in effectively managing power density and routing resources, especially with the rise in the number of intellectual property macros.
Innovation Solution
A routability-driven macro-aware power planning method that divides the chip into sub-regions based on macro locations, determines optimal vertical power stripe widths and numbers using dynamic programming, and adjusts power stripe placements to minimize voltage drop and routing congestion, allowing for more flexible and efficient power mesh design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power mesh is allocated over top two metal layers with HPSs and VPSs, then voltage drop is reduced, but routing area and congestion increase
Solution Approach 1:
The chip is divided into multiple sub-regions based on macro locations, with each sub-region having independently optimized VPS configurations. This segmentation allows localized power planning that reduces overall routing area while maintaining voltage drop performance through region-specific optimization.
Solution Approach 2:
Different sub-regions are assigned different VPS configurations based on their specific macro density and power requirements. The effective power stripe width is locally optimized for each sub-region, allowing areas with high macro density to have wider power stripes while low-density areas use narrower stripes, thus reducing total routing area while maintaining where needed.
2Reliability
If manual power planning is performed by experienced designers, then power delivery is optimized, but complexity and time consumption increase with hundreds of macros
Solution Approach 1:
Macros are pre-placed on the chip before power planning, and their locations are used to define sub-region boundaries. This preliminary action provides structured input for automated algorithms, reducing the complexity of power planning while maintaining optimized power delivery through macro-aware region decomposition.
Solution Approach 2:
The power planning system automatically determines VPS configurations, effective power stripe widths, and locations using algorithms that process macro locations and power requirements. This self-service automation handles the complexity of hundreds of macros without requiring manual designer intervention, reducing both time consumption and human resource requirements.
3Ease of manufacture
If VPSs are aligned across adjacent sub-regions, then manufacturing simplicity is improved, but routing flexibility and resource effectiveness decrease
Solution Approach 1:
VPS alignment is made dynamic rather than fixed - VPSs are aligned within each sub-region but can have different positions in adjacent sub-regions. This dynamic approach allows the power network to adapt to local macro distributions, improving routing resource effectiveness while maintaining manufacturability through consistent alignment rules within each region.
Solution Approach 2:
The chip is segmented into sub-regions with independent VPS alignment references. Each sub-region can have its VPSs aligned to local features rather than requiring global alignment, which improves routing flexibility and resource utilization while maintaining manufacturing simplicity through localized alignment standards.
Data Source
AI summary
A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.