Macro-Block Parallel Video Decoder for Load Balancing
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Solution Overview
Problem
Current MPEG-2 video decoding technologies face challenges in achieving high-speed processing while balancing processor load and reducing data dependency, especially in real-time applications, with hardware implementations being costly and software implementations struggling with power consumption and adaptability.
Innovation Solution
A macro-block level parallel implementation of an MPEG-2 video decoder using a shared or distributed memory system, where a master node decodes Discrete Cosine Transform (DCT) coefficients and distributes them to multiple slave nodes for parallel Inverse Discrete Cosine Transform (IDCT) and motion compensation, reducing data dependency and optimizing communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware implementation is used, then real-time processing requirement is met, but development cost and time-to-market increase
Solution Approach 1:
The patent segments the video decoding process into independent macro-block units that can be processed in parallel by multiple processors. Each macro-block contains independent DCT coefficients and motion compensation data, allowing divide-and-conquer processing that reduces overall complexity while maintaining real-time performance.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by adding a temporal dimension. Multiple processors work simultaneously on different macro-blocks, effectively multiplying the processing capacity without increasing the complexity of individual processing units.
2Adaptability or versatility
If software implementation is used, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent divides the software processing into segmented macro-block tasks that can be distributed across multiple processors. This segmentation allows the system to process video data in parallel, reducing the computational burden on individual processors and thereby lowering overall power consumption while maintaining software adaptability.
Solution Approach 2:
The patent implements partial parallelization where not all processing steps need to be parallelized, but the critical path (macro-block processing) is parallelized to achieve sufficient speedup. This partial action approach balances power consumption reduction with adaptability requirements.
3Productivity
If parallel processing is implemented, then processing throughput is improved, but data dependency among processors increases
Solution Approach 1:
The patent segments the video stream into independent macro-blocks, each containing self-contained DCT coefficients and motion compensation information. This segmentation minimizes data dependencies between parallel processors because each macro-block can be processed independently without requiring frequent inter-processor communication.
Solution Approach 2:
The patent extracts essential data (DCT coefficients and motion vectors) from the bitstream and pre-processes them into macro-block units before distribution to processors. This extraction and pre-processing reduces the amount of data that needs to be communicated between processors during parallel execution.
4Ease of operation
If master-slave architecture is used, then load balancing is improved, but communication traffic increases
Solution Approach 1:
The patent segments the processing workload into uniform macro-block units that are distributed to slave processors. This segmentation enables effective load balancing because each macro-block represents a standardized processing task, and the master processor can distribute tasks based on current system load conditions.
Solution Approach 2:
The master processor performs preliminary actions by pre-decoding the bitstream into macro-block units and preparing all necessary data (DCT coefficients, motion vectors) before distribution to slave processors. This preliminary processing reduces the communication burden during parallel execution because most data preparation is completed beforehand.
Data Source
AI summary
A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the decoded DCT coefficients, and multiple slave nodes/processors for parallel implementation of Inverse Discrete Cosine Transform (IDCT) and motion compensation at the macro-block level. Also provided is a method for macro-block level video decoding in a parallel processing system.