Dummy Boundary Cell Gate Lengths for Macro Channel Routing
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Solution Overview
Problem
In integrated circuit (IC) design, existing methods for inserting dummy boundary cells to minimize device degradation during semiconductor wafer manufacturing are inefficient, leading to potential defects and violations of design rules, especially in the placement and routing of macros and channels.
Innovation Solution
The method involves using different types of dummy boundary cells corresponding to specific gate lengths to form macro boundaries, with these cells being strategically placed around main patterns and in gaps between macros, and swapping them in the channel to ensure optimal placement and compliance with design rules, utilizing Electronic Design Automation (EDA) tools for verification and modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy boundary cells are inserted to minimize device degradation, then manufacturing reliability is improved, but device complexity increases
Solution Approach 1:
The dummy boundary cells are segmented into different types based on gate length (first type with first gate length, second type with second gate length). This segmentation allows the patent to address manufacturing reliability issues at different boundary locations with appropriately sized cells, while maintaining systematic control over the added complexity through standardized cell categories.
Solution Approach 2:
Different types of dummy boundary cells are placed at different locations based on local requirements. The first type of dummy boundary cell is placed at first locations and the second type at second locations, allowing the design to optimize manufacturing reliability locally while maintaining overall design manageability.
2Manufacturing precision
If different types of dummy boundary cells with different gate lengths are used, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent changes the gate length parameter of dummy boundary cells based on their type and location. First type dummy boundary cells have a first gate length while second type dummy boundary cells have a second gate length. This parameter variation improves manufacturing precision by matching cell dimensions to specific design requirements, while the systematic classification keeps complexity manageable.
3Reliability
If dummy boundary cells are placed around macros and in channels, then IP protection is improved, but area occupied increases
Solution Approach 1:
The patent places dummy boundary cells strategically around macros and in channel regions where they are most needed for IP protection and manufacturing reliability. Rather than uniformly filling all available space, the approach uses partial action by placing cells only where required, thus improving protection while minimizing area occupation.
Data Source
AI summary
Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.