Macro Clock Latency Computation in Multi-Iteration CTS
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Solution Overview
Problem
Conventional clock tree synthesis (CTS) methods face challenges in handling macros with large internal clock latency, leading to sub-optimal pin insertion delays and significant area degradations due to the lack of consideration for hold timing and skew in macro clock latencies, resulting in high total negative slack and increased design complexity.
Innovation Solution
A multi-iteration CTS process is implemented, where target pin insertion delays for macros are computed using linear programming in a first iteration, and these delays are used in a second iteration to generate an optimized clock tree, improving setup and hold timing, and reducing total negative slack through incremental adjustments to the clock network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CTS methods are used to build clock trees, then clock distribution is achieved, but macro clock latency is not optimized leading to large hold timing violations and high total negative slack
Solution Approach 1:
The patent computes target macro clock latencies before performing clock tree synthesis in a preliminary iteration. These pre-computed target latencies are then used as constraints during the actual CTS process, allowing the clock tree to be built with optimized macro timing from the outset rather than requiring post-processing corrections.
Solution Approach 2:
The patent introduces target macro clock latencies as an intermediary parameter that mediates between the clock source and macro sinks. This intermediary value is computed through linear programming and serves as a guiding constraint during CTS, enabling optimized clock distribution without directly modifying the physical clock network structure.
2Manufacturing precision
If uniform pin insertion delays are applied to macros, then CTS implementation is simplified, but timing optimization is sub-optimal resulting in large area degradations
Solution Approach 1:
The patent computes individual target clock latencies for each macro sink based on its specific timing requirements and position in the clock network. This localized optimization approach replaces uniform pin insertion delays with macro-specific target latencies, achieving superior timing precision while minimizing the additional area required for buffering and routing.
Solution Approach 2:
The patent transforms the fixed uniform pin insertion delay parameter into variable target macro clock latencies that are computed through linear programming. This parameter change allows each macro to receive customized latency values optimized for its specific timing needs, improving overall timing precision without proportionally increasing design area.
3Reliability
If manual tuning of pin insertion delays is performed, then some timing constraints can be satisfied, but the process is time-consuming and yields sub-optimal results with high total negative slack
Solution Approach 1:
The patent implements an iterative CTS process where the first iteration computes target macro clock latencies based on initial timing analysis, and the second iteration uses these targets to build an optimized clock tree. This feedback loop automatically refines the timing optimization without requiring manual intervention, significantly reducing tuning time while achieving superior timing constraints satisfaction.
Solution Approach 2:
The system performs automatic computation of target macro clock latencies through linear programming and uses these computed values to self-optimize the clock tree synthesis. This self-service approach eliminates the need for manual tuning by engineers, automatically achieving optimal timing results that would otherwise require extensive manual effort and expertise.
4Reliability
If post-CTS stages are used to correct timing violations, then hold timing can be improved, but runtime is significantly increased and design area degrades
Solution Approach 1:
The patent addresses hold timing violations in the preliminary iteration by computing target macro clock latencies that explicitly account for hold timing requirements. By resolving timing issues before the main CTS process, the need for time-consuming post-CTS correction stages is eliminated, maintaining both high reliability and productivity.
Solution Approach 2:
The patent skips the traditional multi-stage sequential process by integrating hold timing optimization into the initial target latency computation. This allows the design flow to rush through to the final optimized clock tree in a single integrated process rather than spending excessive time in multiple correction stages, significantly improving design runtime while maintaining timing reliability.
Data Source
AI summary
Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.