Macro Placement Method for Semiconductor Chip Sub-Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electronic design automation (EDA) placement methods are inefficient in handling floating preplaced macros and a large number of macros, leading to suboptimal performance in terms of wirelength, timing, congestion, and runtime.
Innovation Solution
A method of macro placement that involves partitioning the semiconductor chip into sub-regions, determining a packing sequence for movable macros, extracting search points from placed blocks, defining feasible regions, and evaluating a legalizing cost function to optimize macro placement and reduce runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional EDA placement methods are used, then placement can be performed, but efficiency deteriorates when handling floating preplaced macros and large number of macros
Solution Approach 1:
The chip area is divided into multiple sub-regions, and macros are partitioned into different groups based on their characteristics (floating macros, preplaced macros, movable macros). This segmentation allows each sub-region and macro group to be handled independently, improving placement efficiency for large-scale designs with many macros.
2Loss of time
If conventional EDA placement methods are used, then placement can be performed, but runtime increases for large-scale designs
Solution Approach 1:
The method performs preliminary actions by determining packing sequences for macro groups before actual placement, pre-calculating feasible regions for macros, and establishing placement priorities in advance. This preliminary organization reduces the computational complexity during the actual placement phase, thereby reducing runtime for large-scale designs.
3Reliability
If conventional EDA placement methods are used, then basic placement can be achieved, but handling of floating preplaced macros deteriorates
Solution Approach 1:
The method introduces feasible regions as intermediary structures that mediate between floating preplaced macros and the chip boundary. These feasible regions act as buffer zones that constrain and guide the placement of floating macros, ensuring they are properly positioned without violating design rules, thereby improving both reliability and adaptability.
4Manufacturing precision
If conventional EDA placement methods are used, then simple placement can be performed, but optimization of wirelength and congestion deteriorates
Solution Approach 1:
The method applies different placement strategies and cost functions to different sub-regions and macro groups based on their local characteristics. For example, floating macros in congestion-prone areas receive different treatment than preplaced macros in sparse regions. This localized optimization improves wirelength and congestion metrics while handling large-scale designs effectively.
Data Source
AI summary
A method of macro placement includes partitioning an entire region of a semiconductor chip into sub-regions; determining a packing sequence of a plurality of movable macros in the sub-region; extracting search points of a plurality of placed blocks in the sub-region with respect to one of the movable macros; determining a feasible region associated with the search point; packing said movable macro in the feasible region; evaluating a legalizing cost function; and determining whether a value of the evaluated legalizing cost function is less than a predetermined threshold value.