Macroscalar Vector Processing with Runtime Dependency Checks

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Solution Overview

Problem

Conventional vector processors face limitations in vectorizing loops due to dependencies between iterations, such as loop-carried data dependencies and memory-address aliasing, which restrict the extent of parallelism that can be determined at compile-time, leading to reduced code vectorization and performance benefits.

Innovation Solution

The introduction of recurrent increment and decrement instructions that allow a processor to receive a basis vector and a control vector, selecting a basis value and performing fixed-value addition or subtraction operations based on the control vector, enabling dynamic parallelism and vectorization of loops at runtime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the compiler performs static analysis to determine parallelism during compilation, then the code vectorization can be guaranteed to be safe, but the extent of parallelism that can be determined is limited, reducing code vectorization

Engineering Contradiction:
Improvevectorization safetyVSAvoidcode vectorization extent
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The compiler performs preliminary static analysis to identify potential parallelism and generates vectorized code with embedded runtime dependency checks. This preliminary action prepares the code structure for vectorization while deferring the final safety determination to runtime, allowing the compiler to attempt vectorization of loops that would otherwise be rejected

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention introduces dynamic runtime checks that evaluate loop-carried dependencies and memory-address aliasing at execution time rather than requiring static determination. The vectorized code includes runtime predicates that adaptively determine whether vectorization is safe for each iteration, enabling the system to dynamically adjust between scalar and vector execution based on actual runtime conditions

Inventive Principle:
Principle #15Dynamics

2Reliability

If the processor executes scalar loop iterations sequentially to handle dependencies, then correctness is maintained, but execution time increases and performance benefits are reduced

Engineering Contradiction:
Improveloop execution correctnessVSAvoidloop execution time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The loop execution is segmented into multiple paths: vectorized iterations for independent loop iterations and scalar iterations for dependent ones. The runtime dependency checks partition the loop iterations dynamically, allowing the majority of independent iterations to execute in parallel vectorized form while only the necessary dependent iterations execute sequentially

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the execution parameter from fixed scalar mode to adaptive hybrid mode by introducing runtime predicates that determine the execution mode for each iteration. These predicates evaluate dependency conditions and dynamically switch between scalar and vector execution, optimizing the balance between correctness and performance based on actual runtime data

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9342304B2Processing vectors using wrapping increment and decrement instructions in the macroscalar architecture
Publication Date: 2016.05.17 APPLE INC
  • US9342304B2 patent drawing
  • US9342304B2 patent drawing
  • US9342304B2 patent drawing

AI summary

Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a fixed-value addition operation dependent upon the input vector and the control vector.