Magnetic Array Transistor Merging for Integration Density
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Solution Overview
Problem
Existing magnetic arrays for next-generation nonvolatile memories, such as MRAM, require a large area for multiple transistors to control read and write currents, leading to inefficiencies in integration and increased size.
Innovation Solution
A magnetic array design that includes a substrate, units with magnetoresistance effect elements, switching elements, and specific wiring configurations, allowing for efficient integration by reducing the area required for transistor control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple transistors are used to control read and write currents in spin elements, then the control functionality is achieved, but the area required increases and integration efficiency decreases
Solution Approach 1:
The patent merges the control functions of multiple transistors into a single transistor by combining the read current control and write current control into one switching element. This single transistor simultaneously controls both current paths, eliminating the need for separate transistors and thereby reducing the area required while maintaining full control functionality.
Solution Approach 2:
The single transistor in the invention serves multiple functions: it controls both the read current and write current, acting as a universal control element. This multi-functional approach allows one transistor to replace what would traditionally require two separate transistors, thus reducing area while preserving operational capability.
2Ease of operation
If multiple transistors are used to individually control read and write currents, then precise current control is achieved, but device complexity increases
Solution Approach 1:
The patent combines multiple control functions into a single transistor, reducing device complexity from multiple transistors to one. The single transistor maintains precise control over both read and write currents through its gate terminal, which can selectively control current flow paths based on applied voltage, thereby preserving control precision while simplifying the overall device structure.
3Ease of operation
If a large area is allocated for transistor control, then sufficient control capability is ensured, but integration density decreases
Solution Approach 1:
By merging multiple control functions into a single transistor, the patent significantly reduces the area required for control elements. This area reduction directly increases integration density, allowing more memory cells to be packed into the same chip area while maintaining full control capability through the multi-functional single transistor.
Solution Approach 2:
The patent utilizes three-dimensional stacking of memory layers to compensate for the reduced horizontal area. By implementing magnetic tunnel junctions in multiple stacked layers, the system achieves high integration density vertically while using minimal transistor area horizontally, effectively transitioning from two-dimensional area expansion to three-dimensional volume utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed magnetic array achieves enhanced integration efficiency, allowing for higher recording density and simplified manufacturing processes, thereby addressing the limitations of existing technologies.
Implementation Method 1
A resistance value of a magnetoresistance effect element varies depending on a difference in relative angle between directions of magnetizations of two magnetic films sandwiching a non-magnetic layer therebetween.
Implementation Method 2
attention is focused on spin-orbit torque magnetoresistance effect elements utilizing a spin-orbit torque (SOT)
Implementation Method 3
magnetic domain wall displacement type magnetic recording elements utilizing displacement of a magnetic domain wall
Data Source
AI summary
This magnetic array includes a substrate, a first unit, a second unit, a word line, a first read line, a second read line, a first gate line, a second gate line, and a source line. Each of the units includes a magnetoresistance effect element, a first switching element, and a second switching element. The magnetoresistance effect element includes a laminate and a wiring provided on the laminate. The first switching element is connected to a reference layer of the laminate. The second switching element is connected to the wiring. Each of the read lines is connected to the first switching element. The word line is connected to the second switching element. The gate lines are respectively connected to the first switching element and the second switching element of different units. The source line is connected to the wiring.